Senior Eva/video Design Engineer - Cork jobs at Qualcomm in Ireland, Cork
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Industry experience ASIC or Logic Design, verification, or relevant work experience. Industry experience with Verilog, SystemVerilog. Experience with C/C++, Python/Perl. Experience covering Micro-architecture, RTL Design, Design timing/area/power optimizations, RTL synthesis....
Applies knowledge and experience to architect, design, implement, the testbench to verify the structure and performance computer vision IPs. Creates and maintains verification test benches and environments in System Verilog/UVM....
Industry experience ASIC or Logic Design, verification, or relevant work experience. Industry experience with Verilog, SystemVerilog. Experience with C/C++, Python/Perl. Experience covering Micro-architecture, RTL Design, Design timing/area/power optimizations, RTL synthesis....
Applies knowledge and experience to architect, design, implement, the testbench to verify the structure and performance computer vision IPs. Creates and maintains verification test benches and environments in System Verilog/UVM....
Collaborate closely with video design, performance, firmware, and SW teams to deliver emulation-based solutions for video core verification. Architect and develop test bench infrastructure in C/C++ and Systemverilog for enabling...
Extensive work experience in timing related activities and responsibilities such as library, LVF, AOCV/POCV/SOCV …etc. Experience in CAD tools including correlation between different timing sign-off tools vs. Spice simulation across...
Comprehensive knowledge of interconnect protocols such as APB, AHB, AXI, ACE, ACE-Lite, and NoC concepts. Expertise in diverse integration tasks, including VIP Configuration, Register Model, and Design Debug Features. Strong...
Industry experience ASIC or Logic Design, verification, or relevant work experience. Industry experience with Verilog, SystemVerilog. Experience with C/C++, Python/Perl. Experience covering Micro-architecture, RTL Design, Design timing/area/power optimizations, RTL synthesis....
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