Senior Software System Architect jobs at Nvidia in India

What you will be doing:

• Architect multi-GPU system topologies for scale-up and scale-out configurations, balancing AI throughput, scalability, and resilience.

• Define, modify and evaluate future architectures for high-speed interconnects such as NVLink and Ethernet co-designed with the GPU memory system.

• Collaborate with other teams to architect RDMA-capable hardware and define transport layer optimizations for GPU-based large scale AI workload deployments.

• Use and modify system models, perform simulations and bottleneck analyses to guide design trade-offs.

• Work with GPU ASIC, compiler, library and software stack teams to enable efficient hardware-software co-design across compute, memory, and communication layers.

• Contribute to interposer, package, PCB and switch co-design for novel high-density multi-die, multi-package, multi-node rack-scale systems consisting of hundreds of GPUs.

What we need to see:

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or equivalent area.

• 8 years or more of relevant experience in system design and/or ASIC/SoC architecture for GPU, CPU or networking products.

• Deep understanding of communication interconnect protocols such as NVLink, Ethernet, InfiniBand, CXL and PCIe.

• Experience with RDMA/RoCE or InfiniBand transport offload architectures.

• Proven ability to architect multi-GPU/multi-CPU topologies, with awareness of bandwidth scaling, NUMA, memory models, coherency and resilience.

• Experience with hardware-software interaction, drivers and runtimes, and performance tuning for modern distributed computing systems.

• Strong analytical and system modeling skills (Python, SystemC, or similar).

• Excellent cross-functional collaboration skills with silicon, packaging, board, and software teams.

Ways to stand out from the crowd:

• Background in system design for AI and HPC.

• Experience with NICs or DPU architecture and other transport offload engines.

• Expertise in chiplet interconnect architectures or multi-node fabrics and protocols for distributed computing.

• Hands-on experience with interposer or 2.5D/3D package co-design.

We are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's and many other leading technologies deployed in our Tegra chips.

What you will be doing:

You will be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit:

• Architect the testbenches and craft verification environment using UVM methodology

• Define test plans, tests and verification infrastructure for modules, clusters and system

• Build efficient and reusable bus functional models, monitors, checkers and scoreboards

• Implement functional coverage and own verification closure

• Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust

What we need to see:

You should be BTech/MTech with 5+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs:

• CPU verification, Memory controller verification, Interconnect verification

• High Speed IO verification (UFS/PCIE/XUSB)

• 10G/1G Ethernet MAC and Switch

• Bus protocols (AXI/APB)

• System functions like Safety, Security, Virtualization and sensor processing

• Experience in the latest verification methodologies like UVM/VMM

• Exposure to industry standard verification tools for simulation and debug is a requirement

• Exposure to Formal verification would be excellent

• Good debugging and analytical skills.

• Good interpersonal skills, ability to work as an excellent teammatewith e

What you'll be doing:

• Design and build unified security services for NVIDIA Security Platform, integrating detection, orchestration, and automated response capabilities.

• Partner with product engineering, security architecture, and cloud infrastructure teams to embed secure design patterns and automation across private, public, and emerging AI-native clouds.

• Build secure cloud architecture and implement full-stack solutions—from backend APIs (Java/Spring Boot, Python) to observability portals, and security action workflows—delivering reliability, scalability, and operational excellence.

• Foster process-as-code leadership to transform manual workflows into consumable, automated self-service subscriptions to reduce software vulnerability exposures.

• Together, we evaluate new CSP and third-party security offerings, prototype custom solutions aligned with NVIDIA’s global standards, and continuously supervise environment posture through industry standard benchmarks, logging, and alerting.

• Build vulnerability assessment platforms to automate discovery, prioritization, and remediation workflows, employing AI models with dynamic risk analysis.

What We Need to See:

• Bachelor’s degree or equivalent experience in Computer Science, Engineering, or related field with 8+ years' software development experience.

• Proven experience designing, developing, and deploying services on public or hybrid private-public cloud platforms (AWS, GCP, Azure, OCI).

• Proficiency in Java (Spring Boot) and Python, with a strong grasp of scalable REST API development. Experience building front-end applications using React / Angular,TypeScript/JavaScript,HTML5/CSS. Knowledge of connecting UI and API for secure, high-performing systems.

• Experience implementingInfrastructure-as-Code(IaC), securing containerised and K8S environments (EKS, AKS, GKE, OKE), and integrating monitoring and alerting systems (Grafana, Prometheus, Datadog, PagerDuty) for operational visibility.

• Proven understanding of authentication and authorization protocols (SSO, SAML, Federated Identity, RBAC, IAM policies) in multi-cloud environments to implement secure identity management practices.

• Demonstrated ability to collaborate effectively across global engineering teams, driving secure production-grade solutions through clear communication and cross-functional teamwork.

Ways to Stand Out from the Crowd:

• Bring experience with AI or ML pipelines, especially integration of automated or intelligent security controls—using AI to improve detection, response, or compliance capabilities.

• Demonstrate hands-on work with security and asset platforms, event streaming (Kafka, Pub/Sub), or large-scale data ingestion and analytics (Databricks, Delta Lake).

• Show comfort operating across multiple cloud service providers and hybrid or private environments, applying sophisticated observability, telemetry, and alerting techniques to strengthen security at scale.

We are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's and many other leading technologies deployed in our Tegra chips.

What you will be doing:

You will be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit:

• Architect the testbenches and craft verification environment using UVM methodology

• Define test plans, tests and verification infrastructure for modules, clusters and system

• Build efficient and reusable bus functional models, monitors, checkers and scoreboards

• Implement functional coverage and own verification closure

• Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust

What we need to see:

You should be BTech/MTech with 5+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs:

• CPU verification, Memory controller verification, Interconnect verification

• High Speed IO verification (UFS/PCIE/XUSB)

• 10G/1G Ethernet MAC and Switch

• Bus protocols (AXI/APB)

• System functions like Safety, Security, Virtualization and sensor processing

• Experience in the latest verification methodologies like UVM/VMM

• Exposure to industry standard verification tools for simulation and debug is a requirement

• Exposure to Formal verification would be excellent

• Good debugging and analytical skills.

• Good interpersonal skills, ability to work as an excellent teammatewith e

What you'll be doing:

• Verify Switch design's architecture and micro-architecture using advanced methodologies.

• Build reference models, verify and simulate chip blocks/entities according to specifications.

• Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

• You are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure, test plans and tests and verify the correctness of the design at SOC level.

• Use sophisticated verification methodologies like e-specman, SV-UVM etc.

What we need to see:

• BS (or equivalent experience) / MS with 5+ years of experience in design verification.

• Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).

• Perl/python scripting language experience desirable.

Ways to stand out from the crowd:

• Prior experience of Ethernet or InfiniBand Switches, and/or smartNICs or DPUs, and/or high-speed interconnects.

• Strong debugging, problem-solving and analytical skills.

• Scripting knowledge (Python/Perl/shell).

• Good social skills and ability & desire to work as an excellent teammate.

What you'll be doing:

• Take ownership and drive customer issues on system software, server diagnostics and containers

• Develop features and tools as part of solution engineering efforts to support all Enterprise Service offerings including, but not limited to NGC, Container Orchestrators (such as Kubernetes), GPU accelerated applications

• Build upon the opportunity to research new use cases with GPUs for emerging container technologies

• Bring independent analysis, communication, and problem-solving to customer experience

What we need to see:

• BS in Computer Science, Computer Engineering, or related field (or equivalent experience)

• At least 5+ years system software development and troubleshooting experience, ideally with some customer facing

• Intellectual curiosity, positive attitude, flexibility, analytical ability, self-motivation, and team-oriented

• Strong computer science concepts and excellent knowledge of C/C++, Python and scripting methodologies

• Deep understanding of at least two of the following: data centers, servers, distributed systems, virtualization, server diagnostics, embedded systems

• You'd have cultivated a deep Linux knowledge, and be very comfortable working in various Linux environments as well as with Windows OS’s

• Professional-level communication skills, interpersonal skills with a passion to solve problems

Ways to stand out from the crowd:

• Proven experience in developing, triaging and debugging on Linux, system software, server diagnostics and Containers

• Experience working with distributed systems especially container orchestrators

• Any exposure to system level debug and triaging experience