Senior Solutions Architect - Generative Ai jobs at Nvidia in India, Bengaluru

What you will be doing:

• Architect multi-GPU system topologies for scale-up and scale-out configurations, balancing AI throughput, scalability, and resilience.

• Define, modify and evaluate future architectures for high-speed interconnects such as NVLink and Ethernet co-designed with the GPU memory system.

• Collaborate with other teams to architect RDMA-capable hardware and define transport layer optimizations for GPU-based large scale AI workload deployments.

• Use and modify system models, perform simulations and bottleneck analyses to guide design trade-offs.

• Work with GPU ASIC, compiler, library and software stack teams to enable efficient hardware-software co-design across compute, memory, and communication layers.

• Contribute to interposer, package, PCB and switch co-design for novel high-density multi-die, multi-package, multi-node rack-scale systems consisting of hundreds of GPUs.

What we need to see:

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or equivalent area.

• 8 years or more of relevant experience in system design and/or ASIC/SoC architecture for GPU, CPU or networking products.

• Deep understanding of communication interconnect protocols such as NVLink, Ethernet, InfiniBand, CXL and PCIe.

• Experience with RDMA/RoCE or InfiniBand transport offload architectures.

• Proven ability to architect multi-GPU/multi-CPU topologies, with awareness of bandwidth scaling, NUMA, memory models, coherency and resilience.

• Experience with hardware-software interaction, drivers and runtimes, and performance tuning for modern distributed computing systems.

• Strong analytical and system modeling skills (Python, SystemC, or similar).

• Excellent cross-functional collaboration skills with silicon, packaging, board, and software teams.

Ways to stand out from the crowd:

• Background in system design for AI and HPC.

• Experience with NICs or DPU architecture and other transport offload engines.

• Expertise in chiplet interconnect architectures or multi-node fabrics and protocols for distributed computing.

• Hands-on experience with interposer or 2.5D/3D package co-design.

We are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's and many other leading technologies deployed in our Tegra chips.

What you will be doing:

You will be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit:

• Architect the testbenches and craft verification environment using UVM methodology

• Define test plans, tests and verification infrastructure for modules, clusters and system

• Build efficient and reusable bus functional models, monitors, checkers and scoreboards

• Implement functional coverage and own verification closure

• Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust

What we need to see:

You should be BTech/MTech with 5+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs:

• CPU verification, Memory controller verification, Interconnect verification

• High Speed IO verification (UFS/PCIE/XUSB)

• 10G/1G Ethernet MAC and Switch

• Bus protocols (AXI/APB)

• System functions like Safety, Security, Virtualization and sensor processing

• Experience in the latest verification methodologies like UVM/VMM

• Exposure to industry standard verification tools for simulation and debug is a requirement

• Exposure to Formal verification would be excellent

• Good debugging and analytical skills.

• Good interpersonal skills, ability to work as an excellent teammatewith e

We are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's and many other leading technologies deployed in our Tegra chips.

What you will be doing:

You will be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit:

• Architect the testbenches and craft verification environment using UVM methodology

• Define test plans, tests and verification infrastructure for modules, clusters and system

• Build efficient and reusable bus functional models, monitors, checkers and scoreboards

• Implement functional coverage and own verification closure

• Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust

What we need to see:

You should be BTech/MTech with 5+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs:

• CPU verification, Memory controller verification, Interconnect verification

• High Speed IO verification (UFS/PCIE/XUSB)

• 10G/1G Ethernet MAC and Switch

• Bus protocols (AXI/APB)

• System functions like Safety, Security, Virtualization and sensor processing

• Experience in the latest verification methodologies like UVM/VMM

• Exposure to industry standard verification tools for simulation and debug is a requirement

• Exposure to Formal verification would be excellent

• Good debugging and analytical skills.

• Good interpersonal skills, ability to work as an excellent teammatewith e

What you'll be doing:

• Verify Switch design's architecture and micro-architecture using advanced methodologies.

• Build reference models, verify and simulate chip blocks/entities according to specifications.

• Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

• You are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure, test plans and tests and verify the correctness of the design at SOC level.

• Use sophisticated verification methodologies like e-specman, SV-UVM etc.

What we need to see:

• BS (or equivalent experience) / MS with 5+ years of experience in design verification.

• Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).

• Perl/python scripting language experience desirable.

Ways to stand out from the crowd:

• Prior experience of Ethernet or InfiniBand Switches, and/or smartNICs or DPUs, and/or high-speed interconnects.

• Strong debugging, problem-solving and analytical skills.

• Scripting knowledge (Python/Perl/shell).

• Good social skills and ability & desire to work as an excellent teammate.

What you'll be doing:

As a member of Aerial RAN team working on AI Native stacks, you will be contributing to

• Develop and Optimize AI / ML modules for functional blocks specifically in wireless signal processing

• Perform literature survey to understand the prior art on AI/ML for RAN

• Analyze and identify the suitable ML architecture for the RAN functions of interest.

• Identify the right ML Architecture, complexity for each of the functional blocks

• Collaborate with multi-functional teams to optimize the OTA performance and compute complexity with DevTech and other business units within NVIDIA

• Benchmarking of OTA performance improvements with AI models and compute needs on different platforms

• Iteratively train, test & modify Model Arch for performance improvements

What we need to see:

• Full time PhD student doing research in the fields of AI and Wireless domains, and able to work as an Intern for at least 6 months or more starting from last week of January 2026

• Thorough understanding of the wireless Layer1/Layer2 functions and algorithm aspects

• Excellent grip on AI and ML concepts, techniques and abreast of latest developments in this field

• Deep understanding of Transformers, CNNs and other ML Architectures and their use cases

• Hands on experience in simulating signal processing algorithms in Matlab and Python.

• Programming skills in C/C++

• Experience in analyzing the problem, identifying the right model architectures. developing Models, Training and Optimization, preferably on signal processing domains

from the crowd:

• Knowledge of CPU, DSP or GPU architecture, as well as memory, I/O and networking interfaces.

• Experience with programming latency sensitive, real-time, multi-threaded applications on CPUs and one or more of GPUs or DSPs or Vector processors.

• Appetite to learn the details of how next generations of GPU will operate and build an outstanding Software-Radio 5G/6G stack that can fully demonstrate their power.

• Familiarity with CUDA programming and NVIDIA GPU Architectures