Design Engineer - Memory Subsystem jobs at Nvidia in India, Bengaluru

What you’ll be doing:

• Own ASIC verification of IP/Cluster for complicated designs in RTL.

• Work with HW architects and designers to make the right implementation choices.

• Interact with the Performance verification teams to augment verification through dynamic simulations and/or Formal verification techniques.

• You will work with the specifications and ensure functional and code coverage of all the RTL which you will verify.

• Partner with and enable FPGA and S/W teams to ensure that S/W is tested.

• Be involved with post-silicon verification and debug.

What we need to see:

• BS / MS or equivalent experience.

• 2+ years of design experience.

• Experience in ASIC verification of complex design units for at least one or two projects.

• Background with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).

• Exposure to System Verilog and UVM based methodology for ASIC verification is highly desired.

Ways to stand out from the crowd:

• Knowledge of Memory controllers or prior experience with verification of IP/clusters involving access to Memory.

• Good debugging and problem solving skills.

• Scripting knowledge (Python/Perl/shell).

• Good interpersonal skills and ability & desire to work as a part of a team.

We are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's and many other leading technologies deployed in our Tegra chips.

What you will be doing:

You will be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit:

• Architect the testbenches and craft verification environment using UVM methodology

• Define test plans, tests and verification infrastructure for modules, clusters and system

• Build efficient and reusable bus functional models, monitors, checkers and scoreboards

• Implement functional coverage and own verification closure

• Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust

What we need to see:

You should be BTech/MTech with 5+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs:

• CPU verification, Memory controller verification, Interconnect verification

• High Speed IO verification (UFS/PCIE/XUSB)

• 10G/1G Ethernet MAC and Switch

• Bus protocols (AXI/APB)

• System functions like Safety, Security, Virtualization and sensor processing

• Experience in the latest verification methodologies like UVM/VMM

• Exposure to industry standard verification tools for simulation and debug is a requirement

• Exposure to Formal verification would be excellent

• Good debugging and analytical skills.

• Good interpersonal skills, ability to work as an excellent teammatewith e

We are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's and many other leading technologies deployed in our Tegra chips.

What you will be doing:

You will be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit:

• Architect the testbenches and craft verification environment using UVM methodology

• Define test plans, tests and verification infrastructure for modules, clusters and system

• Build efficient and reusable bus functional models, monitors, checkers and scoreboards

• Implement functional coverage and own verification closure

• Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust

What we need to see:

You should be BTech/MTech with 5+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs:

• CPU verification, Memory controller verification, Interconnect verification

• High Speed IO verification (UFS/PCIE/XUSB)

• 10G/1G Ethernet MAC and Switch

• Bus protocols (AXI/APB)

• System functions like Safety, Security, Virtualization and sensor processing

• Experience in the latest verification methodologies like UVM/VMM

• Exposure to industry standard verification tools for simulation and debug is a requirement

• Exposure to Formal verification would be excellent

• Good debugging and analytical skills.

• Good interpersonal skills, ability to work as an excellent teammatewith e

We are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's and many other leading technologies deployed in our Tegra chips.

What you will be doing:

You will be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit:

• Architect the testbenches and craft verification environment using UVM methodology

• Define test plans, tests and verification infrastructure for modules, clusters and system

• Build efficient and reusable bus functional models, monitors, checkers and scoreboards

• Implement functional coverage and own verification closure

• Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust

What we need to see:

You should be BTech/MTech with 3+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs:

• CPU verification, Memory controller verification, Interconnect verification

• High Speed IO verification (UFS/PCIE/XUSB)

• 10G/1G Ethernet MAC and Switch

• Bus protocols (AXI/APB)

• System functions like Safety, Security, Virtualization and sensor processing

• Experience in the latest verification methodologies like UVM/VMM

• Exposure to industry standard verification tools for simulation and debug is a requirement

• Exposure to Formal verification would be excellent

• Good debugging and analytical skills.

• Good interpersonal skills, ability to work as an excellent teammatewith e

What you'll be doing:

• Verify Switch design's architecture and micro-architecture using advanced methodologies.

• Build reference models, verify and simulate chip blocks/entities according to specifications.

• Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

• You are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure, test plans and tests and verify the correctness of the design at SOC level.

• Use sophisticated verification methodologies like e-specman, SV-UVM etc.

What we need to see:

• BS (or equivalent experience) / MS with 5+ years of experience in design verification.

• Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).

• Perl/python scripting language experience desirable.

Ways to stand out from the crowd:

• Prior experience of Ethernet or InfiniBand Switches, and/or smartNICs or DPUs, and/or high-speed interconnects.

• Strong debugging, problem-solving and analytical skills.

• Scripting knowledge (Python/Perl/shell).

• Good social skills and ability & desire to work as an excellent teammate.