Gpu Full Chip Random Verification Architect jobs at Nvidia in China, Shanghai

What you’ll be doing:

• Be responsible for running test cases to validate NVIDIA GPU Communications Libraries (NCCL, NVSHMEM, UCX, GDRCopy, GPUDirect RDMA etc).

• Be responsible to automate test cases and maintain the automation scripts.

• Collaborate with Developer, PM, marketing, and engineering teams on crafting test plan and implementing validation.

• You will assist in the architecture, crafting and implementing of SWQA test frameworks.

• Be responsible for code coverage improvement and code complexity optimization.

What we need to see:

• BS or higher degree in CS/EE/CE or equivalent experience

• 5+ years of relevant experience

• Seasoned software QA or software testing background; test infrastructure and strong analysis skills

• Be proficient in scripting language (Python, Perl, bash)

• Solid experience with AI development tools for test development and automation

• Knowledge of basic networking concepts

• UNIX/Linux experience is required

• Experiences in C/C++ is required

• Ability to work independently and leadership skillsas well as experience in using quality mindset to drive improvements

• Proficient oral and written English

Ways to stand out from the crowd:

• Experience with CUDA programming and NVIDIA GPUs

• Knowledge of high-performance networks like InfiniBand, RoCE,etc

• Experience with CSPs(AWS, Google Cloud, Oracle Cloud Infrastructure, Microsoft Azure), andHPC cluster,slurm, ansible, etc

• Prior experience with virtualization technologies (KVM, HyperV, VMWARE, OpenStack, Docker, Kubernetes)

• Experience with Deep Learning Frameworks such as PyTorch, TensorFlow, etc

What you'll be doing:

• Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.

• Develop and share best practices for performing pre-silicon power analysis, Enhance internal power tools and automate best practices

• Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.

• Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.

• Select and run a wide variety of workloads for power analysis, Collaborate with performance and architecture teams to validate performance of the workloads

• Prototype a new architectural feature in Verilog and analyze power.

What we need to see:

• EE, MS or PhD in related fields, or equivalent experience.

• Basic understanding of concepts of energy consumption, estimation, and low power design.

• Familiarity with Verilog and ASIC design principles, including knowledge of logic cells.

• Good verbal/written English and interpersonal skills; much collaboration with design teams is expected.

• Strong coding skills, preferably in Python, C++.

• Ability to formulate and analyze algorithms, and comment on their time complexity and memory consumption.

• Desire to bring data-driven decision-making and analytics to improve our products.

Ways to stand out from the crowd:

• Familiar with the power tools/flow development is a big plus

What you will be doing:

• Develop and optimize the control stack, including locomotion, manipulation, and whole-body control algorithms;

• Deploy and evaluate neural network models in physics simulation and on real humanoid hardware;

• Design and maintain teleoperation software for controlling humanoid robots with low latency and high precision;

• Implement tools and processes for regular robot maintenance, diagnostics, and troubleshooting to ensure system reliability;

• Monitor teleoperators at the lab and develop quality assurance workflows to ensure high-quality data collection;

• Collaborate with researchers on model training, data processing, and MLOps lifecycle.

What we need to see:

• Bachelor’s degree in Computer Science, Robotics, Engineering, or a related field;

• 3+ years of full-time industry experience in robotics hardware or software full-stack;

• Hands-on experience with deploying and debugging neural network models on robotic hardware;

• Ability to implement real-time control algorithms, teleoperation stack, and sensor fusion;

• Proficiency in languages such as Python, C++, and experience with robotics frames (ROS) and physics simulation (Gazebo, Mujoco, Isaac, etc.).

• Experience in maintaining and troubleshooting robotic systems, including mechanical, electrical, and software components.

• Physically work on-site on all business days.

Ways to stand out from the crowd:

• Master’s or PhD’s degree in Computer Science, Robotics, Engineering, or a related field;

• Experience at humanoid robotics companies on real hardware deployment;

• Experience in robot hardware design;

• Demonstrated Tech Lead experience, coordinating a team of robotics engineers and driving projects from conception to deployment.

What you’ll be doing:

• Analyze state of the art DL networks (LLM etc.), identify and prototype performance opportunities to influence SW and Architecture team for NVIDIA's current and next gen inference products.

• Develop analytical models for the state of the art deep learning networks and algorithm to innovate processor and system architectures design for performance and efficiency.

• Specify hardware/software configurations and metrics to analyze performance, power, and accuracy in existing and future uni-processor and multiprocessor configurations.

• Collaborate across the company to guide the direction of next-gen deep learning HW/SW by working with architecture, software, and product teams.

What we need to see:

• BS or higher degree in a relevant technical field (CS, EE, CE, Math, etc.).

• Strong programming skills in Python, C, C++.

• Strong background in computer architecture.

• Experience with performance modeling, architecture simulation, profiling, and analysis.

• Prior experience with LLM or generative AI algorithms.

Ways to stand out from the crowd:

• GPU Computing and parallel programming models such as CUDA and OpenCL.

• Architecture of or workload analysis on other deep learning accelerators.

• Deep neural network training, inference and optimization in leading frameworks (e.g. Pytorch, TensorRT-LLM, vLLM, etc.).

• Open-sourceAIcompilers (OpenAI Triton, MLIR, TVM, XLA, etc.).

What you’ll be doing:

In this role you will work closely with deep learning compiler developers to verify new and state of the art deep learning related features and components including implementing and executing functional and performance testing and benchmarking software solutions. This would include implementing verification programs, tools, scripts, and libraries. You will apply deep learning and other sophisticated techniques to implement compiler verification solutions.

What we need to see:

• Pursuing BS/MS/PhD in Computer Science, Computer/Electrical Engineering, Mathematics or equivalent program.

• Strong Python programming skills

• Strong modern C++ programming skills

• Good understanding of machine learning domain and concepts, including Large Language Models (LLM)

Ways to stand out from the crowd:

• Knowledge of deep learning frameworks such as Pytorch, Scikit Learn, JAX/XLA or TensorRT

• Background of other programming languages and domains such as CUDA, Docker and GPU-Accelerated Cloud

delivers industry-leading AI scale-up and scale-out performance withtechnology plus semi-custom ASICs or CPUs. NVIDIA is seeking a Senior

What you'll be doing:

• Responsible for ASIC design verification for various IPs at IP and SOC levels

• Responsible for reference model development and integration

• Participate in IP/SOC architecture, micro-architecture reviews, interface with Architecture, SW/FW, Design, and Modeling to work out comprehensive first-time right verification plans

• Contribute to the innovative verification methodology development, functional and code coverage closure.

• Work on the complex TB creation, direct/random tests and drive the function and coverage to closure.

• Contribute to the development of silicon and platform verification strategy and methodology

• Triage the fail on SOC level with SOCV/EMU/SW team

• Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection, and IP licensing

What we need to see:

• Clear understanding of complexities involved with various design verification tools, including Synopsys VCS or Cadence Xcelium Simulator, Verdi, JasperGold or VC Formal

• Track record of first-pass success in ASIC Development

• B.S. or M.S. degree in Computer Engineering or Electrical Engineering

• Experience working across multiple projects and adjusting priorities in partnership with stakeholders

• 5+ years of experience owning processing ASIC, IP or SoC design verification

• Experience managing and delivering complex mixed language UVM and C++ testbenches

• Ability to interpret functional specs and creating comprehensive test plans

• Ability to write directed and constraint random test to achieve coverage-driven verification closure

• Strong programming skills in C++/SystemC. Familiar with the GDB debugging.

• Experience developing tools and infrastructure using Perl or Python

Ways to stand out from the crowd:

• Hands-on experience with AMBA protocols such as AXI, ACE, CHI, etc.

• Hands-on experience with complex subsystems in new technologies like ARM CPU complex, LPDDR, HBM, GPU’s, UCIE, PCIE or Network on chip and with performance verification