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What You Can Expect
• Lead DV, emulation and post silicon validation execution with zero defect mindset.
• Define DV, emulation and post silicon validation scope.
• Define execution timelines working closely with stakeholders.
• Set goals, monitor, and take steps to keep the execution on track.
• Define DV methodology and verification strategies.
• Drive definition and implementation of DV TB architectures.
• Collaborate with Architecture, Design, DFT, PD, FW and system teams for successful product execution.
• Lead tool evaluation and selection.
• Drive continuous productivity improvements through incremental and forklift changes.
• Monitoring industry DV trends and adapting to key trends.
• Hire, build and retain high performance engineering team.
• Address continuous training and development needs of the team.
What We're Looking For
• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience.
• Strong understanding of ASIC development process.
• Proven ability to lead ASIC development teams.
• Demonstrated track record of delivering high quality ASICs.
• Good understanding of SoC architecture, processor cores, memory, and peripheral interfaces.
• Excellent communication, interpersonal and presentation skills.
• Strong cross-functional leadership skills.
• Highly motivated, self-driven and curiosity to learn new technologies.
Expected Base Pay Range (USD)
203,000 - 300,480, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
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What You Can Expect
What We're Looking For

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What You Can Expect
Provide the instructions to the layout engineers.
Working with the AE for the IP characterization and validation.
What We're Looking For
Master’s degree or PhD in Electrical Engineering
Strong knowledge on the deep sub-micron CMOS technologies.
Experience in designing mixed signal circuits including ADCs, DACs, RX, TX, PLLs, Filters, Bandgap bias circuits, regulators, and other analog circuits.
Knowledge and Experience on low power and high-speed design techniques.
Excellent problem solving, and analytical skills are essential.
Strong knowledge on IC design CAD tools such as Spectre, Spice, Matlab, Hsim, Verilog, etc.
Lab testing skills to evaluate the prototype unit to the design specification.
Expected Base Pay Range (USD)
128,160 - 192,000, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

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What You Can Expect
As a Hardware and Silicon Validation Staff Engineer at Marvell, you’ll be helping to deliver high bandwidth over long distances.
teams such as digital, analog, firmware, to develop Marvell’s next gen,high-speed networking PHY Serdes IP/ICs.
Work independently and collaboratively in post-silicon validation team, to collect, analyze massive data from bench and drive tuning parameters in silicon to ensure product’s quality.
Characterize electrical parameters and building blocks such as Tx jitters, CDR loops, CTLE, PLL, etc.
Tune internal circuitries such as peaking, bandwidth, FIFO, and adaptation algorithms to optimize product’s operating margin at stressed PVT conditions.
Involve in system level hardware (PCB schematics) and work with SI and layout teams to build engineering boards.
Create, maintain and own bench automation libraries (python) for various of products.
As system engineering team at Marvell, we value your ideas and your work will have a direct impact to the product of company.
What We're Looking For
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience.
Experience in following domains is required – Post-Si Validation, Stress & PVT testing.
Strong analog/mixed-signal knowledge.
Solid understanding of modern high-speed PHY/Serdes.
Solid programming skill in languages such as Python, Matlab, etc.
Strong teamwork and communication skills.
Demonstrates good analysis and problem-solving skills.
Expected Base Pay Range (USD)
102,880 - 154,100, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

Share
What You Can Expect
• Lead DV, emulation and post silicon validation execution with zero defect mindset.
• Define DV, emulation and post silicon validation scope.
• Define execution timelines working closely with stakeholders.
• Set goals, monitor, and take steps to keep the execution on track.
• Define DV methodology and verification strategies.
• Drive definition and implementation of DV TB architectures.
• Collaborate with Architecture, Design, DFT, PD, FW and system teams for successful product execution.
• Lead tool evaluation and selection.
• Drive continuous productivity improvements through incremental and forklift changes.
• Monitoring industry DV trends and adapting to key trends.
• Hire, build and retain high performance engineering team.
• Address continuous training and development needs of the team.
What We're Looking For
• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience.
• Strong understanding of ASIC development process.
• Proven ability to lead ASIC development teams.
• Demonstrated track record of delivering high quality ASICs.
• Good understanding of SoC architecture, processor cores, memory, and peripheral interfaces.
• Excellent communication, interpersonal and presentation skills.
• Strong cross-functional leadership skills.
• Highly motivated, self-driven and curiosity to learn new technologies.
Expected Base Pay Range (USD)
203,000 - 300,480, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
These jobs might be a good fit