Principal Sw/fw Engineer jobs at Marvell in Canada, Ottawa

What You Can Expect

Thewill be responsible for designing, simulating, and analyzing high-speed electrical & optical systems and components. This includes the development of optical models, the integration of photonic devices with electronic systems, and optimizing performance for high-bandwidth and low-latency applications. You will play a key role in advancing optical communication technologies, helping drive the next generation of optical interconnects, co-packaged optics, and high-performance networks.

Modeling and Simulation of Optics Drivers:

Develop models for high-speedused to drive(e.g.,,VCSELs).

Model the electrical characteristics of optical drivers to ensure the proper transmission of high-speed signals to optical modulators.

Focus on key parameters like,, andrise/fall timeto achieve the required data rates (e.g., 100 Gbps or higher).

Simulate the performance of the optical driver under various operating conditions, including temperature variations and voltage fluctuations.

Transimpedance Amplifier (TIA) Modeling:

Develop models for, which convert the photocurrent generated by photodetectors (e.g.,,avalanche photodiodes (APDs)) into a voltage signal.

Model key aspects of TIAs, including,,, andto ensure high sensitivity and low distortion.

SerDes I/O System Modeling:

Develop accurate and efficient models for high-speed SerDes interfaces, focusing on both the transmitter and receiver.

Use simulation tools (e.g.,,,) to simulate the performance of SerDes systems in both ideal and non-ideal conditions.

Signal Integrity Analysis:

Perform signal integrity simulations, including,, andfor SerDes I/O interfaces.

Educational Background:

• A PhD or Master’s degree in Optical Engineering , Electrical Engineering , or a related field with significant experience in optical communications and high-speed systems.

Experience:

• Proven experience (typically 10+ years) in high-speed SerDes modeling, Optucal modelling, signal integrity analysis, and I/O system design.
• Experience working with high-speed communication protocols such as PCIe, Ethernet is a MUST.
• Experience with SerDes I/O performance at speeds of100 Gbps, 200Gbps and beyond is highly preferred.
• Experinece with modelling of Opto electronic components such as Silicon Photonics Driver, TIA is highly preferred

Programming and Tools:

• Proficiency in programming languages such as Python , C++ , or Matlab for automation, data analysis, and creating custom simulations.
• Experience with simulation tools (e.g., Cadence , Keysight ADS , Synopsys HSPICE ) for circuit and system-level modeling of high-speed I/O systems.

Expected Base Pay Range (USD)

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

What You Can Expect

• In this position the candidate will be required to check the quality of IP models, decide that it meets the requirements needed by the internal Marvell design teams and investigate different types of failures to comply.
• Additionally the candidate will be learning to use existing Automation Tools and Methodology Design flows in order to support the teams using them.
• Verify the quality and completeness of incoming IP deliverables and investigate different types of failures.
• Develop and maintain automation for IP onboarding.
• Provide support for other CAD developed Tools and Implementation Flows to the Marvell design community.
• Develop and maintain Quality Assurance (QA) related automation software.
• Collaborate with the local and international teams.

What We're Looking For

• Bachelor’s degree in Electronics, Computer Science or related fields and at least 1-3 years of related professional experience.
• Good understanding of IP model formats (SPICE, LEF, GDS, LIB, etc.).
• Knowledge of IP quality requirements for ASIC design.
• Experience in using layout viewer tools.
• Experience in using some of Netlist to GDS digital implementation and signoff flows.
• Scripting experience in tcl/bash/python language.
• User level knowledge of the Unix operating system.
• Desire to learn ASIC design domain concepts to understand the scope of the automations.
• Knowledge about software testing principles.
• Good level of English (spoken and written).
• Good analysis and problem-solving skills.