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Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.
Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Bachelors degree in Computer Engineering, Electrical Engineering or STEM related field with 3+ years of relevant work experience
-OR- Masters degree in Computer Engineering, Electrical Engineering or STEM related field with 2+ years of relevant work experience
-OR- PhD degree in Computer Engineering, Electrical Engineering or STEM related field
Relevant experience should include the following:
Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
PV convergence (including static timing and power analysis)
Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)
Demonstrated success in one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP
Preferred Qualifications:
2+ years of industry experience/exposure with CPU Micro-Architecture
Experience with Physical design best known practices concerning floor-planning, routing techniques, clock distribution
Experience with of Static Timing Analysis, Noise analysis, and reliability verification techniques
Experience with of RTL to GDS methodologies and formal equivalence
Experience with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.These jobs might be a good fit

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What Makes This Role Exciting:This position requires a compressed work-week schedule and full on-site presence—no remote or hybrid options.
Schedule:Compressed work schedule (2–4-day workweek, primarily overnight hours
Key Responsibilities:
Be a Problem-Solving Hero: Provide technical troubleshooting and operational support for Factory Automation Applications, Databases, andPlatforms/Infrastructurein Intel Foundry's Technology Development Factories.
Drive Global Impact: Deliver next-level support for Intel applications across our worldwide factory network.
LeadInnovation: Executeproject work including software installation activities, automation software product hardening, and CIP software development.
Thrive in Our Dynamic Environment:You'll excel in a fast-paced setting where adaptability and flexibility are your superpowers. Quickly master business models to solve complex problems and troubleshoot systems that support factory applications tracking material, controlling semiconductor processing, and analyzing data critical to manufacturing success.
What We're Looking For:The ideal candidate embodies these exceptional traits:
Outstanding problem-solving and interpersonal skills.
Excellent written and verbal communication abilities.
Enthusiasm for cross-geographical collaboration to achieve remarkable results.
Minimum Qualifications:
U.S. citizenship required
Ability to obtain and maintain US Government TS Security Clearance and SCI access.
Bachelor's degree with 3+ years in a STEM discipline.
1+ years of experience in Java, Python, C#, or other object-oriented programming languages.
1+ years of experience in Semiconductor Process Engineering, Semiconductor Manufacturing, or Factory Automation.
Preferred Qualifications:
Master's degree in a STEM discipline .
3+ years of experience in Factory Automation.
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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Your responsibilities will include but not be limited to:
Adding support for new features/IPs into existing emulation models
Learning architecture and microarchitecture by debugging failures to the root cause
Developing high level (for example, C++/Python) modeling for RTL components
Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design
Building multiple emulation targets for an SoC
Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models
System level validation tasks such as using evaluation boards and FPGAs
SOC level feature enabling/debug
The ideal candidate should exhibit the following behavioral traits:
Problem-solving skills
Ability to multitask
Strong written and verbal communication skills
Ability to work in a dynamic and team-oriented environment
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must have a Bachelor’s Degree in Computer Science, Computer Engineering or Electrical Engineering with 3+ years of relevant experience -OR- Master’s Degree in Computer Science, Computer Engineering or Electrical Engineering 2+ years of relevant experience
Preferred Qualifications
Experience with reading and interpreting technical specs and Register Transfer Level (RTL) code
Experience with validation or testing experience, especially in a silicon design team
Experience with UNIX or Linux
Experience with IA-32 assembly and/or Verilog programming experience
Experience writing BFMs
offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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You Are
Your responsibilities may include but not be limited to:
SoC, clock design, and power delivery integration
Drive performance optimization, including co-optimization work with process teams, to create best-in-class designs.
Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.
Static timing analysis constraint understanding and generation, clock stamping, and timing closure.
Multiple Power Domain analysis using standard Power Formats UPF or CPF.
The ideal candidate will exhibit behavioral traits that indicate:
Self-motivator with strong problem-solving skills
Excellent interpersonal skills, including written and verbal communication
Ability to work as part of a team and collaborate in a high-paced
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Bachelor’s Degree in Electrical Engineering, Computer Engineering or a related field with 6+ years of relevant experience -OR- Master’s Degree in Electrical Engineering, Computer Engineering or a related field with 4+ years of relevant
Preferred Qualifications
6+ years of experience in backend design and/or integration product development and delivery on leading edge process nodes
offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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This role's responsibilities include but are not limited to:
You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. This position is not eligible for Intel's immigration sponsorship.
Minimum Qualifications:
Preferred Qualifications:
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Share
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Preferred Qualifications:
Requirements listed would be obtained through hands on industry relevant job experience.
Experienced HireShift 1 (United States of America)US, Oregon, Hillsborooffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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About the Role: We are seeking a highly skilled Senior Engineer with a focus on workload decomposition and a deep understanding of statistics and machine learning algorithms. In this role, you will analyze and decompose workloads to understand their behavior and impact on System-on-Chip (SoC) architecture. You will collaborate with cross-functional teams to ensure our SoCs achieve optimal performance and efficiency, while identifying opportunities for architectural improvements. Additionally, you will drive the development and implementation of simulation methodologies across teams.
Key Responsibilities:
• Workload Decomposition: Lead efforts to decompose and analyze workloads using advanced statistical and machine learning techniques, understanding their behavior and impact on SoC architecture.
• Collaboration: Work closely with architects, design engineers, validation teams, and marketing to deliver industry-leading SoC solutions, providing insights into workload behavior and architectural implications.
• Pre-Silicon Planning: Define and implement detailed tools and methodologies for workload analysis and decomposition in the pre-silicon phase, focusing on architectural design and optimization.
• Simulation Technologies: Establish and implement simulation technologies and methodologies to predict and analyze workload impact on power, performance, and thermal characteristics.
• Simulation Model Development: Develop and refine simulation models that accurately represent workload behavior and its impact on SoC designs, enabling predictive assessments and optimizations.
Extensive experience in simulation development in the pre-RTL phase.
• Strong background in software architecture and quality.
• Proficiency in developing simulation models for SoC.
• Advanced software development skills, including experience with scripting languages such as Python and C++.
Preferred Qualifications:
• Deep understanding and experience with operating systems.
• In-depth knowledge of CPU architecture, benchmarks, power management, and memory sub-system validation.
• Expertise in statistical data analysis and design of experiments.
• Familiarity with industry benchmarks, understanding the aspects of performance they measure, and conducting competitive analysis from previous generation products.
Minimum Qualifications:
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Share
Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.
Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Bachelors degree in Computer Engineering, Electrical Engineering or STEM related field with 3+ years of relevant work experience
-OR- Masters degree in Computer Engineering, Electrical Engineering or STEM related field with 2+ years of relevant work experience
-OR- PhD degree in Computer Engineering, Electrical Engineering or STEM related field
Relevant experience should include the following:
Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
PV convergence (including static timing and power analysis)
Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)
Demonstrated success in one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP
Preferred Qualifications:
2+ years of industry experience/exposure with CPU Micro-Architecture
Experience with Physical design best known practices concerning floor-planning, routing techniques, clock distribution
Experience with of Static Timing Analysis, Noise analysis, and reliability verification techniques
Experience with of RTL to GDS methodologies and formal equivalence
Experience with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.These jobs might be a good fit