Senior Formal Verification Engineer jobs at Intel in Israel, Tel Aviv-yafo

During the last few years, usage of AI based systems and applications is getting wider and wider.

In this role you will:

• Design, develop, and maintain our real-time SW stack.
• Collaborate with cross-functional teams to define software requirements and specifications.
• Optimize software to meet performance requirements, ensure low latency and high reliability.

• B.S. in Electrical Engineering, Computer Engineering, Computer Science, or related.
• Developing experience in Linux environment.
• Proficiency in C++ programming.
• Experience of at least 5 years in SW development.
• Excellent written and verbal communication skills

In addition, excellent candidates may have experience in several of these areas:

• Background in SW development for ASIC.
• Background or experience with GPUs.
• Background or knowledge in Networking.
• Experience with multithreaded programming.
• Experience with runtime performance optimizations.
• Experience in distributed computing, HPC or collective libraries (MPI, NCCL, etc).

Your work will enable scalable, efficient, and high-quality silicon design by leveraging advanced Python software development within modern EDA workflows.

Key Responsibilities:
• Design, develop, and maintain Python-based tools and infrastructure to automate and streamline EDA workflows.
• Develop and extend GitHub Actions/Workflows to support continuous integration, validation, and deployment for hardware design flows.
• Partner with design and CAD teams to identify inefficiencies and deliver high-impact automation solutions.
• Integrate and support EDA tools from major vendors (e.g., Synopsys, Cadence, Siemens) into design flows.

• BS/MS in Computer Science, Electrical Engineering, or related field.
• 5+ years of experience in software development using Python.
• Experience using Git for source control in large collaborative environments.
• Experience using GitHub workflows, including GitHub Actions, secrets, runners, and CI/CD pipelines.
• Strong debugging and problem-solving skills with attention to software robustness and maintainability.

Preferred Qualifications:
• Familiarity with industry-standard EDA tools and front-end design workflows, including RTL development, simulation, functional verification, linting, and logic synthesis.

• Experience using GitHub SDK/API for automation and repository management.
• Familiarity with build systems (e.g., Make, CMake, Gradle) and dependency management.
• Exposure to front-end EDA data formats such as Liberty timing models, SDC constraints, and simulation data formats like SDF and VCD/FSDB.
• Experience designing, deploying, and managing containerized workloads using technologies such as Docker and Kubernetes.

Responsibilities:

• Development and implementation of comprehensive verification plans and strategies for complex hardware designs, ensuring alignment with industry best practices.
• Oversee the maintenance of verification environments using advanced industry-standard tools and methodologies, mentoring junior engineers in the process.
• Review test cases to verify design functionality and compliance with specifications.
• Collaborate closely with design, architecture, and firmware engineers to deeply understand specifications, proactively identifying and addressing potential design flaws during the development process.
• Analyse verification results, derive insights, and effectively communicate findings and recommendations to stakeholders, contributing to strategic decision-making and project direction.

• B.Sc. in Electrical or Computer Engineering.
• 10+ years of proven experience in VLSI chip Verification engineering, with a focus on high-end SoCs and AI applications.
• 3+ years of proven experience in designing cache systems - an advantage.
• Excellent analytical and communication skills, with the ability to effectively collaborate with cross-functional teams in a fast-paced environment.
• Strong motivating and mentorship.
• Strong proficiency in SystemVerilog, UVM, and other verification tools.
• Experience with AI-specific performance benchmarks, NoC performance benchmark and optimization techniques - an advantage.
• Knowledge of system-level scenario analysis and modelling for high-performance SoCs - an advantage.
• Experience with scripting languages (e.g., Python, Perl) for automation and data analysis - an advantage.

Role Description:

• B.Sc. in Electrical Engineering or Computer Engineering.
• At least 10 years of proven experience in Block Level design.
• At least 3 years of proven experience in Cache systems.
• Backend-RTL relevant skills: solving timing paths, restructuring components, area reduction.
• System Verilog – must.
• Soft skills like communication, teamwork, Ownership, accountability , etc.
• Strong analytical and problem-solving skills.

During the last few years, usage of AI based systems and applications is getting wider and wider.

In this role you will:

• Design, develop, and maintain our real-time SW stack.
• Collaborate with cross-functional teams to define software requirements and specifications.
• Optimize software to meet performance requirements, ensure low latency and high reliability.

• B.S. in Electrical Engineering, Computer Engineering, Computer Science, or related.
• Developing experience in Linux environment.
• Proficiency in C++ programming.
• Experience of at least 5 years in SW development.
• Excellent written and verbal communication skills

In addition, excellent candidates may have experience in several of these areas:

• Background in SW development for ASIC.
• Background or experience with GPUs.
• Background or knowledge in Networking.
• Experience with multithreaded programming.
• Experience with runtime performance optimizations.
• Experience in distributed computing, HPC or collective libraries (MPI, NCCL, etc).

You will be part of a team participating in the design of a future generation high performance Intel Atom microprocessors. Also, you will drive physical implementation for a range of memory compilers, custom IPs, and partitions in support of CPU products.

The work is performed with broadly defined parameters and assignments are often complex and nonstandard in nature.

Your responsibilities will include but not be limited to:

• Ensure all designs are following the best practices and are highly efficient.
• Independently perform and drive complex physical design assignments.
• Work closely with circuit design engineers to interpret schematics and drive physical implementation.
• Experience ranging from leaf level cell design to integration is desired.
• Collaborate closely with other SoC projects at various sites across Intel.
• Willingness to develop layout scripts macros and solutions is a plus.

The ideal candidate should exhibit the following behavioral traits:

• Excellent communication and interpersonal skills.
• Prioritization and multitasking skills.
• Good analytical and problem-solving skills.

Minimum qualifications are required to be initially considered for this position,

• Candidate must possess a bachelor's in electronic, Microelectronic Engineering, Computer Engineering, or a related engineering discipline.
• 6+ months of experience in layout design.
• Advanced English level.

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates,

• Master's degree inelectronic/MicroelectronicEngineering, Computer Engineering, or a related engineering discipline.
• 1+ year of experience or familiarity with Very Large Scale of Integration (VLSI) and ComplementaryMetal-Oxide-Semiconductor(CMOS) logic circuit design.
• 1+ year of knowledge in Unix/Linux operating systems.

In this role, you will:

• Design and implement new optimizations within the MLIR and LLVM frameworks to enhance model-level performance for deep learning applications.
• Collaborate with architecture and performance teams to identify and address bottlenecks in the compiler pipeline.
• Engage with internal customers and developers to understand requirements and support model-level performance tuning.
• Explore and prototype novel compilation techniques to improve hardware utilization and efficiency.

Required:
5+ years of experience in C++ and familiarity with modern software development practices.
Background in high-performance computing or parallel programming.
Strong analytical and problem-solving skills.
Experience with development on Linux.Advantage:
Strong experience with compiler design and middle-end optimizations, preferably using MLIR and LLVM.
Experience with code generation, performance analysis, and tuning for hardware accelerators.
Knowledge of dataflow graphs, IR transformation, and optimization techniques.