R&d Engineer Adv Tech Dev jobs at Broadcom in United States, Irvine

Job Description:
 Layout design of digital high-performance blocks
 Timing closure of the blocks with best PPA(power/performance/area)

Ideal Candidate Will Have:
 Strong understanding of physical implementation.
 Experience working with advanced semiconductor technologies.
 Experience in implementing low power and high-performance cores
 Excellent communication and cross-functional collaboration skills.
 Ability to analyze complex trade-offs and make data-driven decisions.
 Master’s degree with 6+ years or PhD with 3+ years of hands-on experience with Place and route tools; PhD in Engineering is a plus

Compensation and Benefits

The annual base salary range for this position is $120,000 - $192,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Responsibilities:

The candidate's main responsibilities include the following:

• Support (50%), enhance, and maintain PDKs and various Analog/Mixed-Signal design tools

• Develop software for automation in Skill, Perl, Unix Shell scripting

• Create documentation and provide hands-on training for design and layout engineers

• Work with EDA vendors to track and resolve issues

• Work with Technology Foundry teams (external/internal) to facilitate debugging and proper characterization of all tool related issues.

Requirements:

• Master in Electrical Engineering or Computer Science + 10 years of EDA experience.

• Expertise in the following CAD Tools: Virtuoso Studio 25.1, Cadence ADE-L/XL, Maestro, Spectre, Virtuoso Layout, Quantus QRC, Voltus-XFi/EMIR, EMX, and Synopsys Hspice, Primesim, StarRC, Quickcap, and Mentor Calibre/PERC

• Solid background in programming skills, circuit design, and device physics knowledge to help solve circuit design, layout, physical verification, and post-layout extraction challenges and problems.

• Experience in all phases of CAD tools from evaluation, QA, test, release, and user support to documentation

• Expert in Cadence Skill, Perl, Unix Shell and utilities

• Excellent interpersonal, communication, and presentation skills, along with strong multi-tasking skills, attention to detail, and the ability to work well in a team

Compensation and Benefits

The annual base salary range for this position is $141,300 - $226,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Job Description:
 Layout design of digital high-performance blocks
 Timing closure of the blocks with best PPA(power/performance/area)

Ideal Candidate Will Have:
 Strong understanding of physical implementation.
 Experience working with advanced semiconductor technologies.
 Experience in implementing low power and high-performance cores
 Excellent communication and cross-functional collaboration skills.
 Ability to analyze complex trade-offs and make data-driven decisions.
 Master’s degree with 6+ years or PhD with 3+ years of hands-on experience with Place and route tools; PhD in Engineering is a plus

Compensation and Benefits

The annual base salary range for this position is $120,000 - $192,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Job Description:
 Layout design of digital high-performance blocks
 Timing closure of the blocks with best PPA(power/performance/area)

Ideal Candidate Will Have:
 Strong understanding of physical implementation.
 Experience working with advanced semiconductor technologies.
 Experience in implementing low power and high-performance cores
 Excellent communication and cross-functional collaboration skills.
 Ability to analyze complex trade-offs and make data-driven decisions.
 Master’s degree with 6+ years or PhD with 3+ years of hands-on experience with Place and route tools; PhD in Engineering is a plus

Compensation and Benefits

The annual base salary range for this position is $120,000 - $192,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Designs and develops SerDes hardware validation platforms. Evaluates SerDes performance at speeds up to 128 Gb/s for PCIE, Ethernet, JESD and CPRI. Serdes RX validation of CTLE, DFE, FFE, PAM4, FEC hardware. SerDes Tx validation for Jitter, SNDR, Phase Noise. Able to perform PCIE calibration using Valiframe BitifEye calibration package and EZJIT and related scope packages. Familiar with Seasim/SigTest calibration packages for PCIe and COM based calibrations for Ethernet/JESD/CPRI. Complete speccompliant SinusoidalJitter Tolerance measurements and Random InterferenceTolerance measurementsusing Keysight M8040 BERT, Infiniium Scopes and PNA.

• Requires in-depth lab experience using high performance test equipment, cables and connectors
• Experience: Bachelors and 8+ years of related experience; at this level a post-graduate degree is typically expected or Masters degree and 6+ years of related experience or PhD and 3+ years of related experience

Compensation and Benefits

The annual base salary range for this position is $108,000 - $172,800

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

• Work with Business Units chip design team & Analog / Digital IP owners (e.g. 224 PAM*, 112G PAM4, HBM2e/3) for new advanced node silicon (7nm, 5nm, 3nm..) chip floor plan & IP bump pattern design and optimization for package design requirements (e.g. layer-count, stack-up, escape architecture, BGA pattern development, s-parameterextraction/comprehensionand optimization [RL, NEXT/FEXT, IL etc.], and power integrity [PI] requirements)

• Work with business unit marketing and IC design teams to select the optimum package solution on cost, performance, manufacturability, and reliability for new advanced silicon node products (7nm, 5nm, 3nm and beyond)

• Work with IC design, system design, package SI/PI & thermal engineering teams to design custom packages

• Ensure designed packages meet CPI, SI/PI, and stringent thermal requirements (1000W+) of advanced node cutting edge silicon products

• Research, develop, and productize new materials such as TIM, build-up-film, underfill etc. in support advanced node silicon (7nm & 5nm) POR definition

• Manage IC packaging activity from concept through development, qualification and high volume production.

• Be a specialist and able to define assembly BOM, process, troubleshoot, support on packaging issues on new advanced technology

• Implement, fine-tune, and productize newly developed technologies into HVM

• Create package design documentation and assembly instructions

• Work close with QA and customers to resolve quality issues

• Interface with packaging assembly and substrate suppliers for new product bring-up, qualification and production ramp

• Interface with other operations functional groups such as product engineering, foundry, test, and QA

• Participate in package technology development and/or other business productivity projects which have broad team impact (e.g. assembly process enhancement, new TIM material development etc.)

• Interface with tier #1 external customers for custom ASIC programs or as needed for development support, quality and/or other issue resolution

Job Requirements

• BS/MS/PHD in MaterialScience/Electrical/MechanicalEngineering

• Experience: 0-2+ years in IC packaging and assembly - Exceptional fresh-out will be considered

• Deep understanding of signal integrity and power integrity concepts such as characteristic impedance, s-parameters (RL, IL, FEXT/NEXT etc.), power plane impedance profile requirements and optimization etc.

• Strong authority on Cadence APD for custom substrate design

• Hands-on expertise of advanced and new assembly processes for flipchip, MCM packages, and 2.5D for advanced node silicon products (7nm, 5nm and beyond)

• Good understanding of materials as related to Chip Packaging Interaction (CPI)

• Familiarity with wafer BEOL as related to CPI (top metal, AP, passivation, UBM, bumping etc.)

• Knowledge of advanced substratemanufacturing/processis a must (e.g. SAP/mSAP, PSPI w/ Cu RDL etc.)

• In depth knowledge of failure analysis techniques on advanced node silicon (7nm, 5nm etc.) products with ELK and MiM structures

• Conceptual knowledge of package cost structure

• Strong project management, communication and leadership skills

• Must have knowledge of GD&T and be able to read/comprehend mechanical drawings

• Good understanding of manufacturing and quality engineering fundamentals (DOE, process capability indices, etc.)

• Job requirements are broad; the candidate must be able to expand and grow in multiple disciplines(manufacturing/quality,materials, electrical, thermal, and mechanical)

• Track record of innovation and subject matter expertise through journal publications and/or patent awards is desired

• Familiarity with advanced technologies such as 2.5D, 3D patterned structures such as inductors in package substrate, substrate technology is a plus

Compensation and Benefits

The annual base salary range for this position is $66,000 - $105,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

single/multi-dimensionedFEC, digital filters, andinterface/integrationwith analog functions.Responsibilities include:• Develop specification, architecture, and micro-architecture of signal processing and communications algorithms• Define and document chip requirements, architecture, verification and lab test plan• Bit-exact MATLAB/Simulink and C/C++/Java system modeling and simulation• Develop and run system level simulations of the transceiver and perform vector matching verification with RTL simulations• Lab testing and debug of ASICs•Documentation/applicationnote development and customer supportRequirements:• Bachelor's + 8 years of related experience, or Master's + 6 years of experience, or PhD + 3 years of experience• Knowledge in Communication Theory and Digital Signal Processing algorithms

• Knowledge of analog circuit behavior, transmission line theory, and s-parameters• Experience in MATLAB/Simulink, C/C++/Java, Python, Unix, Linux• Experience architecting communications systems for high performance ASIC based products is highly desirable• Good hands-on skills in the lab• RTL coding expertise is a plus• Good oral and written communication skills

Compensation and Benefits

The annual base salary range for this position is$107,000 -$171,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.