Staff Soc Design Engineer jobs at Arm in United States, San Diego

• As a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team developing the logic for our reconfigurable Fuse Subsystem.
• Work as part of the design team to understand the Fuse Subsystem requirements, and develop the design specifications which meet the quality, reliability, manufacturing and reconfigurable needs across multiple SoC's.
• Your key responsibilities will include crafting design micro-architecture specifications, developing the RTL, fixing bugs, running design checks and contributing to the generation of implementation constraints.
• Work closely with the verification team to review test plans and help debug design issues in addition to crafting UVM components for IP and SoC integration of the Fuse Subsystem
• As part of the design team, you will contribute to developing and enhancing the design methodologies used by the team
• Mentor and support other members of the team to enable the successful completion of project activities
• Required to work with Project Management to define plans and schedules

In addition to bringing your accomplishment of either Bachelors or Master’s degree in Computer Science or Electrical/Computer Engineering or a similar related field and 5+ years' experience working in design of complex subsystems or SoCs, you will need:

• Experience in digital hardware design for complex systems using System Verilog.
• Experience with working with analog hard IP integration, timing diagrams, BMODs
• Experience with reconfigurable IP / Subsystem design
• Experience with power and clock domain crossing
• Experience with static design checks like linting, CDC/RDC, X-propagation
• Exposure to all stages of design: initial concept, specification, implementation, testing, documentation and support
• Experience collaborating with the verification team on design quality closure
• Experience with Perl, Python or other scripting language
• Leadership, mentoring or coaching experience

• Experience with ARM-based designs and/or ARM System Architectures
• Experience with verification methodologies – UVM
• Experience with UPF, IP-XACT
• Experience leading teams or projects
• Experience developing and integrating subsystems for PCIe, UCIe, DDR/LPDDR/HBM, Ethernet etc.
• Understanding of DFT topics: RTL testability, scan insertion, OCC

We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together. These behaviors are assessed as part of the hiring process:

• Partner and customer focus
• Collaboration and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises

We offer a hybrid approach to home and office working to provide an adaptable experience for all employees. We expect some working time to be spent in office, to promote a strong collaborative environment with good team integration but are accommodating to different home working requirements.

At Arm, the SoC Interconnect Architect defines and designs innovative on-chip interconnect architectures-coherent and non-coherent-for scalable SoC platforms. You will work across markets including mobile, automotive, datacenter, networking, and IoT, contributing to production-quality silicon with top-tier performance and efficiency. Collaborating with multi-functional teams, you'll shape the interconnect infrastructure that powers next-generation SoCs.

• Architect on-chip interconnect solutions (coherent and non-coherent) across a range of silicon products.
• Collaborate with performance, power, and physical design teams to optimize interconnect fabrics.
• Develop SoC architecture using Arm product IP to meet compute performance targets.
• Define interconnect platform roadmaps in partnership with core technology teams.
• Optimize end-to-end platform solutions with software and hardware teams.
• Guide early architecture discussions with customers and partners, delivering ready-to-implement specifications.
• Support use case analysis and performance analysis.
• Drive innovation and continuous improvement in interconnect technologies.

• 8+ years' experience in on-chip interconnect architecture for various silicon products.
• 8+ years' experience with coherency protocols and hierarchical cache design.
• Proven track record working with performance, power, and physical design teams on interconnect solutions.
• Experience designing scalable SoCs across multiple sectors and process nodes.
• Knowledge in areas such as heterogeneous compute, PCIe/CXL, security, caching, memory systems, and packaging.
• Strong communication and leadership skills with executive-level influence.
• Bachelor's or Master's degree or equivalent experience in Electrical or Computer Engineering and 10+ years in semiconductor roles.

• Ability to thrive in dynamic environments with shifting priorities.
• Constructive, strategic mindset to challenge and improve status quo.
• Track record of delivering complex projects on time and to spec.

Arm is proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work collaboratively to defy ordinary and shape extraordinary!

• Partner and Customer Focus
• Collaboration and Communication
• Creativity and Innovation
• Team and Personal Development
• Impact and Influence
• Deliver on Your Promises

• Lead electrical engineering efforts from conceptual studies through design, construction, commissioning, and operation.
• Develop and review electrical design standards and specifications, ensuring alignment with industry standard processes and Arm’s reliability goals.
• Perform detailed engineering analysis (load flow, short-circuit, and arc flash studies).
• Provide direction, coordinate with, and review the designs of external consultants and partners.
• Conduct site inspections and factory acceptance tests (FATs) for critical power infrastructure UPS, switchgear, generators, PDUs, etc.
• Provide guidance on power distribution, grounding, redundancy (N, N+1, 2N), and energy efficient strategies.
• Support operational readiness, maintenance planning, and root-cause analysis of electrical issues impacting uptime.

• Bachelor’s or Master’s degree or equivalent experience in Electrical Engineering.
• Deep technical knowledge of medium and low voltage power systems, power distribution, UPS systems, generators, battery energy storage systems (BESS), power distribution units (PDUs), and other related electrical infrastructure found within data center environments
• Proficiency with electrical modeling tools (SKM Power Tools and ETAP)
• Strong familiarity with NFPA 70 (NEC), NFPA 70E, IEEE, and international electrical codes.
• Excellent communication skills and ability to collaborate in a cross-discipline team.
• Comfortable with a fast-paced environment that is rapidly developing and changing.
• Prior experience with hyperscale data center environments or co-location facilities.

• Professional Engineering (PE) license or equivalent international certification (this position will not be stamping drawings as EOR).
• Previous experience designing for Tier III or Tier IV data centers as defined by Uptime Institute (or comparable levels of design).
• Visio, BlueBeam, AutoCAD, or other design and drafting software.

• Be part of a groundbreaking team influencing the next generation of data center systems!
• Collaborate with premier engineers and vendors to develop industry-leading AI hardware.
• Drive innovation in electrical design at scale with global impact.
• Access professional growth through sophisticated project involvement and multidisciplinary teamwork.
• Join a company committed to diversity and inclusion, where your work matters and drives global progress!

You will be working on accelerating ML across a variety of next generation Arm IP.

As part of this role, you will get to work on exciting projects related to functional and performance modeling and analysis - like modeling a new feature in our in-house models, workload characterization, analyzing performance, or developing tools on automation and visualization of the results.

• Functional or performance modeling experience for Hardware IP development
• Strong software development skills including experience with modern C++ and Python
• Strong problem solving and debugging skills
• Strong computer architecture and systems engineering fundamentals
• Good analysis and presentation skills
• Familiarity with Linux development

• Experience with Machine Learning IP development / systems
• Experience with cache-coherent memory system architecture
• Hardware microarchitecture exploration experience

As a verification engineer, you will make a difference by influencing the verification strategy and methodology, taking ownership of complex work packages and driving them to success.

• Meticulous attention to detail, ensuring high-quality verification that minimizes bug escapes.
• Shown experience in block-level verification using UVM or similar methodologies.
• Strong knowledge of coverage driven verification for complex designs.
• Proficient in specifying, creating, and debugging SystemVerilog/UVM constrained-random testbenches.
• Skilled in planning verification tasks and producing realistic effort and time estimates.

• Experience in working with requirements definition and management.
• Formal verification experience.
• Proficiency in developing C/C++ models of a microarchitecture.
• Familiarity with Arm architecture and AMBA bus protocols.
• Experience with CI platforms and version control tools.
• Practical knowledge of machine learning and neural networks.

• Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC
• Analyze design timing, area and power to help improve the quality of ARM IP
• Develop and deploy new methodologies to improve implementation efficiency and results
• Support and develop detailed implementation analysis and data-mining methodologies.
• Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.
• Converting R&D concepts into real implementation solutions.
• Enable our partners to achieve the best possible quality of results.

• Bachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.
• 7+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification
• The ability to demonstrate that you can express new insights and communicate them effectively. Possess a high level of dedicated, initiative and problem-solving skills.
• Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams
• Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Proven programming and scripting skills eg. Tcl, Perl, R, Make, sh.

• Knowledge around Arm based CPUs and SoCs!
• Experience with low power design techniques (power gating, voltage/frequency scaling)
• Experience with Verilog RTL design.
• Experience with ATPG tools/and or production testing.

We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding!

• Partner and customer focus
• Teamwork and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises

You will be working on accelerating ML across a variety of next generation Arm IP.

As part of this role, you will get to work on exciting projects related to functional and performance modeling and analysis - like modeling a new feature in our in-house models, workload characterization, analyzing performance, or developing tools on automation and visualization of the results.

• Functional or performance modeling experience for Hardware IP development
• Strong software development skills including experience with modern C++ and Python
• Strong problem solving and debugging skills
• Strong computer architecture and systems engineering fundamentals
• Good analysis and presentation skills
• Familiarity with Linux development

• Experience with Machine Learning IP development / systems
• Experience with cache-coherent memory system architecture
• Hardware microarchitecture exploration experience