Senior Cpu Architect jobs at Arm in India, Bengaluru

Job Overview:

Responsibilities:

Required Skills and Experience:

We Prefer graduate or postgraduate from a university or Engineering School, in Electronic Engineering or equivalent Engineering Degree.

· You have 4-8 years of experience in SRAM/memory designs, margin analysis, characterization and verification

· You have some understanding of computer architecture and concepts.

· We expect you to have basic understanding of CMOS Transistors, their behaviors.

· We expect some basic understanding of high speed/low power CMOS circuit design, clocking scheme, static and complex logic circuits.

· Understanding of Power versus Performance versus Area trade-offs in typical CMOS design.

· You have an engineering demeanor and Passion for Circuit design.

· Expected to have good interpersonal skills.

“Nice To Have” Skills and Experience:

· You know basic scripting languages, e.g. Perl/TCL/Python.

· Some Experience of working on Cadence or Synopsys flows.

· Experience with Circuit Simulation and Optimization of standard cells.

· Silicon debug/validation

In Return:

Responsibilities

• As a creative design engineer with a knowledge of subsystems and SoCs you will be part team developing Subsystems & SoCs.
• You will work with Architects to capture the requirements and develop Micro-architecture specifications for one or more SOC areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc.
• Key responsibilities will include writing micro-architecture and work with Design team to deliver high quality RTL.
• Collaborate with verification and Validation team to review test plans, and help debug design issues. Closely work with the Power and Performance analysis team to evaluate and improve Subsystem/SOC PPA.
• Contribute to developing and improving the design methodologies.
• Guide and support other members of the team for overall Program success. Balance other opportunities such as working with Project Management on activities, plans, and schedules

Required Skills and Experience:

• Bachelors or Master’s degree or equivalent experience in Electronics/Electrical Engineering.
• Experience of 8+ years working in design of complex compute subsystems or SoCs
• Expertise in developing Micro-architecture and Design specifications for the SoC Infrastructure areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc.
• Solid understanding of digital hardware design and Verilog HDL. Experience in development and Tapeout of Complex SoC and RTL Development.
• Experience leading and developing RTL for Subsystems or SoCs.
• Conversant with Lint, CDC and RDC flows.
• Good communication (written, verbal, presentations) skills.
• Experience with Perl, Python or other scripting language

Desired Skills and Experience:

• Experience with ARM-based designs and/or ARM System Architectures
• Experience developing subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet
• Experience with SystemVerilog and verification methodologies – UVM/OVM
• Experience leading small teams or projects
• Experience or knowledge in the following areas
• Synthesis and timing analysis
• Static design checks, including CDC, RDC, X-Propagation, Linting
• Power management techniques
• DFT and physical implementation

• Define, implement, and maintain methodologies for CDC, RDC, Lint, and CLP analysis.
• Ensure RTL quality through static analysis, debugging, and architectural alignment.
• Collaborate with design teams to interpret specifications and resolve RTL/System Verilog issues.
• Support and maintain flows for analyzing infrastructure IPs and NoC architectures.
• Automate static checks and integrate them into development flows using Python scripting.
• Handle and collaborate using version control systems like Git.

• Expertise in static analysis tools for CDC, RDC, Lint, and CLP.
• Strong experience in delivering clean, high-quality RTL code.
• Ability to interpret and implement architectural and functional specifications.
• Familiarity with infrastructure IPs and Network-on-Chip (NoC) designs.
• Solid understanding of RTL design and debugging with System Verilog.
• Proficiency in Git for version control.
• Scripting experience in Python for tool automation and flow improvement.

• Exposure to front-end integration tools and design methodologies.
• Strong interest and skill in flow development and automation.
• Experience with IP management using IPXACT.
• Understanding of behavioral and synthesized model correlation.

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence
• Deliver on your promises

Job Overview:

It would also be desirable if you have experience with media, graphics or imaging flows and driver/middleware stack development.

Responsibilities:

• Design and implement software components that meet functional safety requirements (e.g., ISO 26262, IEC 61508).
• Work to bring function safety to existing code.
• Develop and maintain documentation to support safety certification and compliance audits.
• Collaborate with safety engineers, hardware teams, and software architects to define software safety requirements and architectures.
• Support software integration, verification, and validation processes in safety-critical systems.
• Contribute to process improvements and tooling for safety-focused software development workflows

Required Skills and Experience:

• Strong proficiency in C development, particularly in embedded or system-level programming.
• Well-versed in functional safety principles, including hazard analysis, safety goals, and ASIL decomposition.
• Motivation and ability to work on frontend tasks using JavaScript.
• Hands-on experience with safety standards such as ISO 26262 or IEC 61508.

“Nice To Have” Skills and Experience :

• Experience with safety analysis tools and methods (e.g., FMEA, FMEDA, fault injection).
• Knowledge of MISRA C/C++ or other safety-related coding standards.
• Background in developing software for automotive, aerospace, or industrial control systems.
• Familiarity with safety certification processes and documentation requirements.
• Knowledge of media, imaging or rendering pipelines.

In Return:

As part of the methodology team, you will lead the development, improvement, and deployment of low power structural check methodologies across multiple SoC and IP projects. This role involves designing automated flows for UPF/CPF consistency, power domain integrity, and structural rule validation at both RTL and netlist levels. You will collaborate closely with design, verification, and EDA partners to ensure robust, scalable, and high-coverage power-aware design signoff strategies across technology nodes and product segments.

• Develop and maintain low-power structural check methodologies (UPF/CPF validation, isolation, level shifters, retention, domain crossings).
• Build automated flows using tools like Synopsys VC LP, SpyGlass-LP, and Conformal LP.
• Ensure power intent consistency and early issue detection through collaboration with design and verification teams.
• Integrate structural checks into signoff regressions with high coverage and low false positives.
• Work with vendors and internal teams to enhance tools, debug issues, and improve efficiency.
• Drive global adoption through documentation, training, and support.
• Assist in audits, quality reviews, and milestone checks.

• 5+ years of Strong background in low-power structural methodologies and UPF/CPF-based flows.
• Deep understanding of power intent specs, domain partitioning, isolation, and retention.
• Hands-on experience with tools like VC LP, SpyGlass-LP, or Cadence CLP.
• Skilled in scripting (Python, Perl, TCL) for flow automation.
• Experience with large SoC/IP designs across advanced nodes.
• Confirmed ability to debug structural issues and drive closure.
• Strong communication and documentation skills.

• Experience with formal verification or functional simulation for power-aware designs.
• Knowledge of complex power analysis and correlation with structural checks.
• Exposure to hierarchical low-power signoff strategies in multi-voltage or multi-power domain SoCs.
• Familiarity with power-aware DFT, scan strategies, and low-power aware synthesis flows.
• Participation in industry working groups (e.g., Accellera UPF), technical conferences, or publications.
• Involvement in tool benchmarking, vendor collaborations, and internal tool qualification projects.

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence
• Deliver on your promises

Arm System IP enables designers to build Arm AMBA systems that are high performance, power efficient and reliable. Configurable for many different applications, System IP is the right choice for your system whether it is a high-efficiency IoT endpoint or a high-performance server SoC.

Our group is seeking dedicated verification engineers to deploy and implement designs and products.

• Build and maintain detailed verification plans/strategies for our next generation interconnect designs.
• Work alongside architects and designers to debug and develop new features balancing the needs of multiple partners in our product development cycle.
• Architect and develop sophisticated and efficient SystemVerilog/UVM based test benches.
• Debug functional regression failures, close coverage and drive improvements.

• Bachelors, Masters or PhD in Electrical/Computer Engineering or Computer Science
• 7+ years of experience in verification/RTL design.
• Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI).
• Previous experience in specification, creation, and debug of System Verilog/UVM constrained-random testbenches.
• Software engineering skills including understanding of object-oriented programming, data structures, and algorithms.
• Proficiency with functional coverage verification methods.

• Knowledge of high speed protocols such as PCI Express (PCIe), SATA, USB and Ethernet.
• Excellent knowledge of scripting languages such as Python or Perl.
• Experience in Formal Verification techniques is a plus.

The purpose of this role is to ensure that various system implementations based on the same architectural specifications, can run standard software from different vendors efficiently and with minimal effort. This will reduce overall market deployment time and enable broad adoption of these system implementations.

Mandatory Skills

- Programming using C/C++/Assembly with experience in software engineering methodologies.

- Software development skills, ideally in the area of firmware / low level operating systems

- Familiar with verification process such as Test Plan development, Test case development

Nice To Have

Familiarity of Unix / Linux working environment, Experience in Linux kernel and UEFI,

- Implementation of bespoke test harness' for O/S and bare metal validation

- Ability to understand and drive complex technical specifications

- Familiarity with EDA tools and Hardware Design Verification/ Emulation based verification