Cdo Vulnerability Manager jobs at Arm in India, Bengaluru

• Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC
• Analyze design timing, area and power to help improve the quality of ARM IP
• Develop and deploy new methodologies to improve implementation efficiency and results
• Support and develop detailed implementation analysis and data-mining methodologies.
• Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.
• Converting R&D concepts into real implementation solutions.
• Enable our partners to achieve the best possible quality of results.

• Bachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.
• 7+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification
• The ability to demonstrate that you can express new insights and communicate them effectively. Possess a high level of dedicated, initiative and problem-solving skills.
• Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams
• Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Proven programming and scripting skills eg. Tcl, Perl, R, Make, sh.

• Knowledge around Arm based CPUs and SoCs!
• Experience with low power design techniques (power gating, voltage/frequency scaling)
• Experience with Verilog RTL design.
• Experience with ATPG tools/and or production testing.

We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding!

• Partner and customer focus
• Teamwork and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises

Arm seeks an experienced Director of Performance Engineering to lead technical strategy and execution for our Userspace, Java Enterprise, Android, and Optimization teams. Reporting to senior leadership, you'll drive key initiatives focused on software performance, optimization, and architectural enhancements across Java-based enterprise applications, Android platforms and userspace environments.

• Provide clear technical leadership for a team of 60+ engineers with 4-5 direct technical leads, across multiple geographical locations.
• Define and drive architectural strategies, performance analysis, and optimization of Java Enterprise and Android userspace software.
• Ensure robust, scalable, and optimised software solutions that enhance user experience and system performance.
• Collaborate effectively with product management, quality assurance, and operational teams to ensure software aligns with business and technical objectives.
• Establish clear technical roadmaps and deliver measurable performance improvements.

• Proven experience leading large-scale Java Enterprise, Android and userspace software development and optimization.
• Strong recent coding background, specifically within Java-based enterprise software, Android application development, or userspace optimization.
• Significant leadership experience, effectively managing teams of 50+ software engineers.
• Deep understanding of software optimization, performance tuning, profiling tools, and practices.

• Familiarity with open-source software ecosystems.
• Knowledge of Arm architecture and the associated software environment.

Job Overview

You will specify and develop new hardware verification testbenches for future generation hardware IP. You will improve existing testbenches to increase performance, quality and efficiency. You will also identify areas for improvement in processes and methodologies, then implement those changes to advance our best-practices for hardware verification. This is a new team with plenty of opportunities to shape its future, and your own growth and career progression.

Depending on prior experience, the responsibilities of the role can include:

• Verification ownership of unit level or multi-unit hierarchy or alternatively verification lead of an overall IP (ISP, Display, Video).
• Architecting verification IP and full verification environments.
• Reviewing and assessing proposed design changes from a verification complexity point of view.
• Analysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and debug.
• Identify cross Media IP process or methodology improvement opportunities, implementing changes to advance hardware verification efficiency.
• Close collaboration with other Arm engineering teams leading to high quality IP that works well in a complete system.
• Mentor & support other members of the team.

• Experience in working with constrained-random verification including ownership of a suitably complex verification environment and creating testbenches.
• Experience developing reusable and scalable code whilst having in-depth knowledge of SV-UVM.
• Strong scripting skills – being able to develop scripts to support new and existing flows.
• Solid software engineering skills including understanding of object-oriented programming, data structures, and algorithms.
• Familiar with the tools and processes for developing testbenches and finishing all aspects of the verification process.
• Prior technical and/or team leadership skills required for more senior positions.

• Team leadership and mentoring experience.
• Multiprocessing microarchitecture experience including knowledge of bus protocols (e.g. AMBA APB/AHB/AXI).
• Past experience in Formal Verification testbenches.
• Experience in video codec, ISP, or display projects, including knowledge of advanced image processing algorithms, such as local tone mapping, noise reduction, motion estimation, transform coding, etc.
• Experience of Functional Safety product development for the Automotive market (applying standards such as ISO 26262 and/or IEC 61508).
• Experience with Continuous Integration flows.

You will get to utilise your engineering skills to build support for the technologies and influence millions of devices for years to come. You will be able to drive and bring your ideas to a wider audience, while building your technical leadership and influencing skills.

• Use knowledge of I/O subsystems and SoCs to integrate PCIe, DDR, and other High-Speed IO IP for SoCs.
• Collaborate within a project team to review architecture and develop design specifications.
• Write micro-architecture specs, develop RTL, fix bugs, and run design checks.
• Work with the verification team to analyse test plans and debug design issues.
• Partner with the performance analysis team to evaluate and improve I/O performance.
• Support backend implementation by aiding floor planning, constraints, and timing closure.
• Contribute to enhancing design methodologies used by the team.
• Guide and support team members to ensure project success.
• Assist Project Management with activities, plans, and schedules.

• Experience in developing and integrating subsystems for PCIe, DDR/LPDDR, HBM, UCIe, Ethernet
• Experience in RTL design for sophisticated SoC development using Verilog and/or SystemVerilog.
• Proficiency in static design checks, synthesis, timing analysis, power management, and power/clock domain crossing.
• Exposure to all design stages: concept, specification, implementation, power/performance analysis, optimisation, testing, documentation, and support.
• Produce specifications and documentation for sophisticated designs.
• Knowledge of shell scripting (e.g., Tcl, Perl, Python, etc.).

• Experience with Arm-based designs and/or Arm System Architectures
• Exposure to interconnect design or architecture
• High level programming experience such as C/C++ and/or assembly language programming
• Experience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures.

As a SoC performance modeling engineer you will be responsible for ensuring the success of these designs by running system level performance analysis much ahead of the RTL and providing feedback to System Architects and IP design leads.

• Engaging with System architects on future systems within Arm.
• Creating full system simulation models using a range of IP performance models from across the company.
• Working with architects and design teams to characterize the system and finding opportunities to optimize configuration.
• Developing exploration models for system components like Coherent and Non-Coherent interconnects, Last Level Caches (LLC/SLC), Multifaceted memory controller (DDR5, LPDDR5/6, HBM etc.)
• Defining and leading investigations that are aimed at benchmarking the efficiency of new IP features in a full system context.
• Building infrastructure to enable better inspection and root-cause analysis of such systems.
• Helping to define future direction of system performance modeling across Arm.

• Experience in developing and using cycle approximate/accurate performance models.
• Experience in generating pre-silicon/pre-RTL performance projections and performance bottleneck debug and analysis.
• Strong C/C++ programming and debugging skills.
• Excellent interpersonal and communication skills.
• Ability to work in teams and to collaborate with colleagues in other groups and sites.
• Proactive and motivated.

• Bachelors, Masters, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science with a strong computer architecture, microarchitecture, performance experience.
• Knowledge of on-chip bus protocols such as AMBA, coherency flows, interconnects, memory subsystems
• Knowledge of CPU microarchitecture.
• Experience in evaluating/benchmarking system level performance using performance monitors.
• Exposure to performance analysis and tuning in pre- and post-silicon environments.