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Cellular Asic Design Integration Engineer jobs at Apple in United States, Irvine
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Irvine
76 jobs found
05.06.2024
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Apple Cellular ASIC Design Integration Engineer United States, California, Irvine
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This position requires thorough knowledge of the ASIC design flow, FE and design verification, synthesis, scripting, and netlist generation. Knowledge of ASIC/SoC design flow. Knowledge of FE tools (CDC, RDC,...
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06.06.2024
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Apple Design Integration Engineer United States, California, Irvine
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Knowledge of the ASIC design flow, synthesis, static timing analysis, scripting, and netlist generation. Understanding of UPF and low-power design & implementation techniques. Hands-on experience in timing/SDC constraints generation, analysis,...
11.06.2024
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Apple ASIC Logic Design Engineer Wireless Group United States, California, Irvine
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5+ years of hands-on experience in ASIC design flow. Solid background in design micro-architecture. Experience in ASIC design front end flows, such as Lint, CDC, STA, LEC. Self-starter, highly motivated,...
29.08.2024
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Apple Camera Image Sensor Analog Design Engineer United States, California, Irvine
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Bachelor's degree and 10+ years of analog design experience. Ability to use industry standard ASIC design tools. Experience with modern design verification techniques in mixed signal environments. Multi-disciplinary understanding of...
04.06.2024
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Apple Senior Digital Integration & Timing Engineer United States, California, Irvine
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BS and 10+ years of relevant industry experience. Knowledge of the entire ASIC design flow from RTL integration through synthesis, static timing analysis, scripting, P&R to tapeout. Expertise in STA...
04.09.2024
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Apple RFIC Layout Engineer United States, California, Irvine
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3+ years of relevant industry experience. Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS (16nm and lower with FinFet experience as a must)....
04.06.2024
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Apple RTL Design Engineer United States, California, Irvine
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Extensive experience in logic design with the following qualifications:. RTL design using Verilog or SystemVerilog, assertion writing. Design of state machines, data paths, arbitration and clock domain crossing logic. Logic...
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Description:Full job details
This position requires thorough knowledge of the ASIC design flow, FE and design verification, synthesis, scripting, and netlist generation. Knowledge of ASIC/SoC design flow. Knowledge of FE tools (CDC, RDC,...
These jobs might be a good fit
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