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Phy Design Verification Engineer jobs at Apple in United States, Cupertino
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Cupertino
1,501 jobs found
04.06.2024
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Apple PHY Design Verification Engineer United States, California, Cupertino
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BS and 3+ years of relevant industry experience. Verification experience of wireless/wired communication block/subsystem. Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and...
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07.09.2024
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Apple Design Verification Engineer United States, California, Cupertino
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Masters’ degree or higher in Electrical Engineering or Computer Science. Extensive course work in digital design and computer architecture. Foundation in object oriented programming techniques. Lab courses or work experience...
24.09.2024
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Apple Design Verification Engineer United States, California, Cupertino
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Knowledge of computer architecture and digital design fundamentals. Knowledge of Verilog or SystemVerilog, digital simulation and debug. Experience with Python, Perl, or similar scripting language. Ability to work independently to...
26.09.2024
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Apple CAD Engineer – Design Verification Tools Infrastructure United States, California, Cupertino
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Experience scripting/coding in Python. Experience in CAD tools and flows. Knowledge of OOP programming languages. Minimum requirement of BS and 10+ years of relevant industry experience. Good analytical skills. Computer...
04.06.2024
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Apple Design Verification Engineer United States, California, Cupertino
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Professional coding skills in Verilog or SystemVerilog. Sophisticated knowledge of standard ASIC design and verification flows including RTL design, simulation and testbench development, coverage analysis and constrained random testing. Advanced...
13.06.2024
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Apple Design Verification Engineer United States, California, Cupertino
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Deep knowledge of SystemVerilog and UVM. Deep knowledge in developing scalable and portable test-benches. Proven experience with verification methodologies and tools such as simulators, waveform viewers. Build and run automation,...
06.06.2024
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Apple Design Verification Engineer United States, California, Cupertino
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Description:Full job details
Extensive knowledge of SystemVerilog test-bench language and UVM. Experience developing scalable and portable test-benches. Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage...
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Description:Full job details
BS and 3+ years of relevant industry experience. Verification experience of wireless/wired communication block/subsystem. Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and...
These jobs might be a good fit
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