Design Verification Engineer jobs at Apple in United States, Cupertino
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United States
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Cupertino
952 jobs found
13.06.2024
A
Apple Design Verification Engineer United States, California, Cupertino
Deep knowledge of SystemVerilog and UVM. Deep knowledge in developing scalable and portable test-benches. Proven experience with verification methodologies and tools such as simulators, waveform viewers. Build and run automation,...
- Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy. - Knowledge of SystemVerilog, digital simulation and debug....
Knowledge of ASIC verification simulation and testbench development flows with SystemVerilog and UVM. Experience with constrained random testing, coverage closure, and RTL / gate simulations. Experience with scripting in languages...
Prior experience with verifying networking chip or complex control logic at subsystem or SoC. Wireless and/or MAC verification experience is a plus. Advanced knowledge of standard ASIC design and verification...
Basic knowledge of computer architecture and digital design. Knowledge of Verilog and Verilog simulators. Knowledge of scripting languages such as Perl. Should be a standout colleague with excellent interpersonal skills...
Basic knowledge of computer architecture and digital design. Knowledge of Verilog and Verilog simulators. Knowledge of scripting languages such as Perl. Should be a standout colleague with excellent interpersonal skills...
Dedicated/hands-on ASIC DV experience. Advanced knowledge of HVL methodology (UVM/OVM) with most recent experience in UVM. Some experience with formal verification is a plus. Proven track record of working full...
Deep knowledge of SystemVerilog and UVM. Deep knowledge in developing scalable and portable test-benches. Proven experience with verification methodologies and tools such as simulators, waveform viewers. Build and run automation,...
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