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Site Reliability Engineer – Software Csg jobs at Apple in United States, Beaverton
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United States
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Beaverton
158 jobs found
14.04.2025
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Apple RTL Design Engineer United States, Oregon, Beaverton
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BS degree in technical discipline with minimum 3 years of relevant experience. Solid understanding of mixed signal concepts, RTL design, Verilog and SystemVerilog. Deep knowledge of front-end tools (Verilog simulators,...
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13.04.2025
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Apple DDR Design Engineer United States, Oregon, Beaverton
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BS degree in technical discipline with minimum 10 years of relevant experience. RTL design using Verilog or SystemVerilog, assertion writing. Design of state machines, data paths, arbitration and clock domain...
13.04.2025
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Apple Mixed Signal Circuit Design Engineer United States, Oregon, Beaverton
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BS degree in technical discipline with minimum 3 years of relevant experience. Proven understanding of all aspects of Analog/Mixed Signal Circuit Design of PHYs. TX, RX, Delay Locked Loops, Phase...
13.04.2025
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Apple SoC Power Modeling Engineer United States, Oregon, Beaverton
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A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience. Our ideal candidate should have relevant experience, programming skills and an...
13.04.2025
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Apple CPU Design Verification Engineer United States, Oregon, Beaverton
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Minimum BS and 3+ years of relevant industry experience. Academic and industry understanding of CPU architecture. Academic and industry knowledge of digital logic design, chip architecture and microarchitecture. Programming knowledge...
13.04.2025
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Apple Physical Design Engineer United States, Oregon, Beaverton
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Bachelors of Science in Electrical Engineering and 10 years experience preferred. The ideal candidate will have deep design experience in high PHY and/or SOC designs. Deep Knowledge about industry standards...
13.04.2025
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Apple SoC DFT Engineer United States, Oregon, Beaverton
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BS and a minimum of 10 years relevant industry experience. Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time....
Description:Full job details
BS degree in technical discipline with minimum 3 years of relevant experience. Solid understanding of mixed signal concepts, RTL design, Verilog and SystemVerilog. Deep knowledge of front-end tools (Verilog simulators,...
These jobs might be a good fit
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