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Ams Layout Designer jobs at Apple in Japan, Minato

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Company (1)
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Japan
Minato
1 jobs found
07.04.2025
A

Apple AMS Layout Designer Japan, Minato

Limitless High-tech career opportunities - Expoint
Typically requires more than 5 years of experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits. Experience implementing analog layouts to achieve tight matching, low noise, and low power...
Description:
You will be responsible to deliver fully-verified, clean layout, this includes the following: - Designing sophisticated layout for mixed signal, and analog circuits in deep sub-micron CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers. - Running complete set of design verification tools available on AMS blocks. - Working with circuit design team to plan/schedule work and negotiate any necessary layout tradeoffs as needed. - Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. - Exceeding engineering specifications and expectations by working closely with the design team. - Applying advanced CAD tools and mask design knowledge to deliver accurate and robust layout that meet stringent matching performance, area and power
  • Typically requires more than 5 years of experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits
  • Experience implementing analog layouts to achieve tight matching, low noise, and low power consumption. Layouts may include analog blocks, resistors, capacitors, pad IOs, ESD structures, etc.
  • High level of proficiency in custom and standard cell based floor-planning and hierarchical layout assembly.
  • Must understand techniques for handling IR drop, RC delay, electro-migration, self heating and coupling capacitance.
  • Must recognize failure prone circuit and layout structures, have experience with analog and DFM standard processes, and proactively work with circuit designer to identify the best approach to solving problems.
  • High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
  • Knowledge of MENTOR GRAPHICS or CADENCE layout tools.
  • Excellent interpersonal skills and able to work with multi-functional teams.
  • English communication with e-mail is required
  • Scripting skills in PERL or SKILL are a plus, but not required
  • Verbal communication in English is considered a plus
  • Bachelors of Science, preferred in Electrical Engineering
Show more
Limitless High-tech career opportunities - Expoint
Typically requires more than 5 years of experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits. Experience implementing analog layouts to achieve tight matching, low noise, and low power...
Description:
You will be responsible to deliver fully-verified, clean layout, this includes the following: - Designing sophisticated layout for mixed signal, and analog circuits in deep sub-micron CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers. - Running complete set of design verification tools available on AMS blocks. - Working with circuit design team to plan/schedule work and negotiate any necessary layout tradeoffs as needed. - Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. - Exceeding engineering specifications and expectations by working closely with the design team. - Applying advanced CAD tools and mask design knowledge to deliver accurate and robust layout that meet stringent matching performance, area and power
  • Typically requires more than 5 years of experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits
  • Experience implementing analog layouts to achieve tight matching, low noise, and low power consumption. Layouts may include analog blocks, resistors, capacitors, pad IOs, ESD structures, etc.
  • High level of proficiency in custom and standard cell based floor-planning and hierarchical layout assembly.
  • Must understand techniques for handling IR drop, RC delay, electro-migration, self heating and coupling capacitance.
  • Must recognize failure prone circuit and layout structures, have experience with analog and DFM standard processes, and proactively work with circuit designer to identify the best approach to solving problems.
  • High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
  • Knowledge of MENTOR GRAPHICS or CADENCE layout tools.
  • Excellent interpersonal skills and able to work with multi-functional teams.
  • English communication with e-mail is required
  • Scripting skills in PERL or SKILL are a plus, but not required
  • Verbal communication in English is considered a plus
  • Bachelors of Science, preferred in Electrical Engineering
Show more
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