Qualcomm FY25 Intern - Scan dump analyzer tool months Guyancourt 

France, Ile-de-France 

274260984

Job Area:

Interns Group, Interns Group > Interim Intern

Qualcomm France’s QITC mission is to develop and deploy highly configurable custom-built interconnect hardware NoC (Network-on-Chip) IPs, software tools, exploration and verification methodologies so that worldwide SoC integration teams can quickly assemble SoCs with the desired Power Performance Area (PPA) characteristics. To this end, QITC technology embraces the complete SoC infrastructure to provide increased SoC performance at minimal cost for integration. Our work is at the backbone of the SoC, interconnecting all major IP solutions. QITC is always searching for new solutions to increase the design and quality of the NoCs micro architecture hence the desire to bring new machine learning technics in the process.

The Snapdragon System on Chips (SoCs) and their integrated Network on Chips (NoCs) are equipped with a scan dump feature, which provides a detailed and comprehensive snapshot of the internal units’ states. Analyzing scan dumps is a time-intensive task that requires significant knowledge of internal NoC units. We aim to develop a tool capable of automatically analyzing scan dumps from Snapdragon NoCs, extracting critical information, processing the states of significant flip-flops, and aiding in the root cause analysis of silicon issues. The intern will work with real scan dumps provided from Snapdragon SoCs. Key objectives of the project include understanding the NoC microarchitecture, identifying the necessary hardware information for critical silicon debugging, defining a workflow to process raw scan dump data, transforming it into meaningful debug data, and highlighting critical information. Additionally, the intern will implement the described workflow to create a brand-new solution for debugging future generations of SoCs

• Initial Training:

o Acquire a good understanding of the existing technology and tools

o Getting familiar with our observation mechanisms

• Core Activity:

o Work with hardware units’ owners to detect meaningful information needed for silicon debug

o Define the metadata from the NoC configuration needed to automatically extract critical silicon debug information o Propose a workflow for an automatic tool that formalizes the analysis process. This tool should take a scan dump as input and provide as output processed data, highlighting clear, concise information to aid in debugging silicon hang/issues.

o Implement the tool

o Test the tool with real scan dumps

• Bonus:

The trainee can develop a GUI for the tool

Final year master’s degree in Microelectronics, Computer Science, or related field Python, bash, Git GUI QT competencies is a plus Some microelectronics knowledge Fully proficient in French and proficient in English

6 months.

Interest for the trainee:

The internship is paid.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.