Cisco ASIC Engineer 

United States, California, San Jose 

49275153

The application window is expected to close on: 5/30/2025

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Minimum Requirements:

Bachelor’s degree +years of related experience, or Master’s degree +years of related experience.

Demonstrated experience in System Verilog and UVM methodology and debugging skills

Prior experience of developing UVM based infrastructure from scratch.

Ability to handle complex features/parts of a chip independently.

Proficient in merging and analyzing code coverage data that is generated by functional simulation

Preferred Qualifications:

The ability to work in a dynamic environment delivering quality work on a tight schedule.

Experience with Forwarding logic/Parsers/P4.

Experience with ASIC design (RTL coding, timing closure, etc.)

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