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Cisco ASIC Design Engineer United States, California, San Jose 934325155
11.03.2025
The application window is expected to close on: March 28, 2025.
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
This role requires being onsite on our San Jose office 4+ days/week.
Your Impact
Key responsibilities:
- Development of high-performance designs/ASICs from specification to tape-out.
- Author micro-architecture specifications and participate in specification and test plan reviews.
- Architect and implement complex RTL designs.
- Implement Verilog RTL to meet timing and performance requirements.
- Analyze code coverage and provide feedback to the verification team to achieve coverage closure.
- Collaborate with the verification and physical design teams to resolve block level issues.
- Perform diagnostic and post silicon validation tests in the lab.
Minimum Qualifications:
- Bachelor’s in Electrical or Computer engineering and 5+ years of ASIC Design experience or Master's degree in Electrical or Computer engineering and 3+ years of ASIC Design experience.
- Verilog/System Verilog programming experience.
- Experience with digital concepts and fundamentals of ASIC design principles.
- Interactive and waveform debug experience.
Preferred Qualifications:
- Experience troubleshooting and debugging.
- Scripting experience (Python, Perl, TCL, shell programming).
- Experience with Networking, networking ASICs, or SoC.
- Good written and verbal communication skills.
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