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Broadcom Design Verification Engineer United States, California, San Jose 312621193
17.12.2024
Job Description:
Job duties:
- Formal and functional verification of complex designs, especially around external interfacing IPs.
- Identify designs that are suitable for formal verification, apply formal verification techniques and perform formal coverage closure.
- Responsible for all aspects of verification from test planning, test bench development, test execution and functional/code coverage closure.
Skills/Expertise:
- Expertise in formal verification.
- Strong understanding of System Verilog assertions and ability to quickly write effective coverage and assertion properties. Ability to understand Verilog designs and develop relevant verification properties.
- Expertise in architecting reusable and constrained random test benches from scratch.
- Verification expertise with Interface IP designs. Beneficial areas would include High bandwidth memory (HBM) PHY / controller sub-systems, Ethernet/PCIE/CXL (Physical coding sublayer)/Serdes designs.
- Experience with external customer support for design IPs or VIPs.
- Expertise in System Verilog especially writing SVAs for formal. Familiar with verificationmethodologies likeUVM.
Minimum Industry Experience :
- Bachelors + 8+ years of related experience.
- Or Masters degree + 6+ years of experience
Compensation and Benefits
The annual base salary range for this position is $107,000 - $171,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
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