Cisco ASIC Design Verification Engineer 

United States, California, San Jose 

5914810

Your Impact

You will contribute to developing Cisco’s revolutionary data center solutions by designing industry-leading complex chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include:

• Architect and develop block, cluster, and top-level DV infrastructure from scratch, including maintaining and enhancing existing environments.
• Create and execute test plans for design qualification at various levels, using a mix of constraint random and directed stimulus.
• Ensure comprehensive verification coverage through code and functional coverage implementation and review.
• Qualify RTL design quality with Gate Level Simulations and support emulation testing.
• Collaborate with cross-functional teams to debug and optimize designs during post-silicon bring-up and manage the ASIC bring-up process.

Minimum Qualifications

• Bachelor’s Degree in EE, CE, or other related field.
• 5+ years of related ASIC design verification experience.
• Proficient in ASIC verification using UVM/System Verilog.
• Proficient in verifying complex blocks, clusters and top level for ASIC.
• Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
• Scripting experience with Perl and/or Python.

Preferred Qualifications

• Master’s Degree in EE or CE.
• Experience with Forwarding logic/Parsers/P4.
• Experience with Veloce/Palladium/Zebu/HAPS.
• Formal verification (iev/vc formal) knowledge.
• Domain experience on one or more protocols (PCIe, Ethernet, RDMA, TCP).