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Nvidia Senior Timing VF Methodology Engineer 
United States, California 
279525254

Yesterday
US, CA, Santa Clara
time type
Full time
posted on
Posted 5 Days Ago
job requisition id

We are seeking an innovative senior timing and VF Methodology engineer to develop pioneering timing sign-off strategies for next-generation GPUs and SoCs. In this role, you’ll optimize performance, yield, and reliability by advancing modeling, analysis, and automation methods. Your work will affect products across AI, graphics, and autonomous vehicles. We're looking for someone passionate about the challenges of deep sub-micron design (3nm and beyond) who thrives on pushing the limits of precision and scalability. You’ll collaborate across teams to shape methodologies that influence the entire future of computing.

What you will be doing:

  • Develop methodologies to bridge the gap between pre-silicon and post-silicon data VF and Vmin.

  • Develop automation to scale V-F curve prediction across multiple projects covering CPUs and GPUs

  • Collaborate with methodology leads, and timing engineers to refine silicon V-F projections to model sub-micron process effects

  • Develop tools, and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer.

  • Work on various aspects of timing analysis and optimization with the goal of achieving best PPA

What We Need To See:

  • MS (or equivalent experience) in Electrical or Computer Engineering with 3+ years’ experience in ASIC Design and Timing.

  • Knowledge of device physics, STA methodology.

  • Good understanding of mathematics/physics fundamentals of electrical design.

  • Exposure to PrimeTime and timing closure derating methodologies

  • Understanding crosstalk, electro-migration, noise, OCV, timing margins. Familiarity with Clocking specs: jitter, IR drop, crosstalk, spice analysis.

  • Understanding of standard cells/memory/IO IP modeling and its usage in the ASIC flow. Hands-on experience in advanced CMOS technologies, design with FinFET technology 5nm/3nm/2nm and beyond.

  • Expertise in coding- TCL, Python. C++ is a plus. Familiarity with industry standard ASIC tools: PT, ICC, Redhawk, Tempus etc.

  • Strong communications skill and good standout colleague

You will also be eligible for equity and .