Nvidia Senior Timing Methodology Engineer 

United States, Texas 

300909100

What You'll Be Doing:

• Improve and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for high-speed designs, with focus on CAD and automation.

• Develop custom flows for validating QoR of ETM models, both of std cells and custom IPs.

• Developflows/recommendations

• Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance.

• Develop tools, and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer.

• Work on various aspects of STA, constraints, timing and power optimization.

What We Need To See:

• MS (or equivalent experience) in Electrical or Computer Engineering with 3 years’ experience in ASIC Design and Timing.

• Good understanding of modeling circuits for sign-off

• Good knowledge of extraction, device physics, STA methodology and EDA tools limitations. Good understanding of mathematics/physics fundamentals of electrical design.

• Clear understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS), CDC, signal/power integrity, etc.

• Understanding of 3DIC, stacking, packing, self-heating and its impact on timing/STA closure.

• Understanding crosstalk, electro-migration, noise, OCV, timing margins. Familiarity with Clocking specs: jitter, IR drop, crosstalk, spice analysis.

• Understanding of standard cells/memory/IO IP modeling and its usage in the ASIC flow. Hands-on experience in advanced CMOS technologies, design with FinFET technology 5nm/3nm/2nm and beyond.

• Expertise in coding- TCL, Python. C++ is a plus. Familiarity with industry standard ASIC tools: PT, ICC, Redhawk, Tempus etc.

• Strong communications skill and good standout colleague