Nvidia Senior Timing Methodology Engineer 

Taiwan, Hsinchu 

940759148

What you'll be doing:

• Initiate and bringup wafer sort ATE program during new product introduction, and ramp up for mass production.

• Deploy new probing technology and methodology, includes machine learning for artificial intelligence model, high bandwidth test fixture for 3D IC support.

• Engage the on-site work with team collaboration, communication, and drive the ATE/probing HW vendor/supplier on right strategy to improve the performance, quality and reliability

• Build up statistical tool or perform data analysis for gap and rootcause analysis.

• Build up statistical widget or performing data analysis for gap analysis and problem solving.

• Create the productivity script tool for test automation, machine learning, and production efficiency.

• Support inline debugging and troubleshooting for the resolution of production line issue.

What we need to see:

• BS or equivalent experience in EE or CS related fields.

• 3 years or above of Advantest 93K experience at test house, ATE vendor, either written wafer sort program or production sustaining.

• Knowledge of Compute Language in either C++/C or VB, Perl, Python is preferred.

• Good command of oral and written English.

• Good communications in collaboration team work.