Intel Lead Customer Support Engineer - Memory 

United States, Texas 

261795971

Job Description:

The responsibilities will include:

• Timely resolution of customer issues related to Memory functionality, Memory timings and Memory usage in SOC's
• Replication, debug of issues either individually or through experts and managing interactions with customers and IP developers to fully understand the issue, provide work arounds and solutions.
• Developing great working relationships with customers and RnD teams.
• Understanding of the competitive landscape and proactive identification of gaps in the FIP offering and proposing solutions to address such gaps. Helping customers boost productivity.
• Identification, prioritization of customer requirements and collaboration with Customer Account Management and RnD functions on developing FIP roadmap and delivering solutions.
• Proactive contribution to customer facing and internal documentation and technical training materials.
• Developing technical presentations, app notes and assisting customers in FIP evaluation.
• Influencing RnD and QA team on ensuring continuous improvement of FIP collateral quality.

Qualifications:

You must possess the minimum qualifications listed below to be considered for this position. Preferred qualifications are not required, but all other things being equal they will give you an advantage in the interview process.

Minimum Qualifications:

• Bachelor’s degree in electrical engineering, computer science or similar engineering field with 10+ years or a Master’s degree and 8+ years of Memory design experience
• Experience working on at least some of the different types of memories (SRAM/ROM/RF/TCAM, eFuse, antiFuse).
• Experience hands on working in all aspects of memory design (circuit design, layout, characterization, views generation, views use, QA) is a must.
• The role would require the person to have in depth working knowledge of different memory architectures and all memory views (gds, oasis, spice, lef, cdl, lib, verilog, atpg, pgv, apl, ndm, mtv, etc.)
• Understands memory integration in SOC and how views are consumed in EDA flows
• Understanding of SoC design utilizing at least one industry standard EDA tool stack (Synopsys, Cadence, Siemens EDA).
• Experience with physical, timing and reliability sign off, including hands on experience is resolving related issues in design.
• Experience presenting to customers and upper management.
• Experience debugging design and EDA workflow issues, combined with experience prioritizing based on deep understanding of the impact on customers.
• Hands on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and antiFUSE.
• Scripting skills, preferably in TCL and Python.

Preferred Qualifications:

• Team leadership experience
• Experience with project management best practices.
• Experience using Jira Service Management and Jira Software platforms.
• Experience prioritizing and dispositioning multiple streams of issues and customers.
• Experience with design and sign off on advanced process nodes.

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, California, Folsom, US, California, Santa Clara, US, Texas, Austin
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