מציאת משרת הייטק בחברות הטובות ביותר מעולם לא הייתה קלה יותר
Apple Design Verification Engineer Japan, Minato 991525678
30.08.2024
Description
Construction of verification environment by using Verilog, System Verilog or UVM Designing test plan for verification Coding test scenarios, assertion and debugging for Digital Design
Minimum Qualifications
- Typically requires a minimum of 5 years of experience in System Verilog or other verification language
- Knowledge of constrained random verification environments.
- Hands-on experience with Assertion Based Verification
- Knowledge with Object Oriented Programming
Preferred Qualifications
- Knowledge of one of verification language (UVM, OVM, or VMM).
- Familiarity with system design using C(C++) or Verilog.
- Basic design background in support of verification results analysis.
משרות נוספות שיכולות לעניין אותך
