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Apple Physical Design Verification Engineer Japan, Minato 43885246
08.02.2025
Minimum Qualifications
- We are looking for experienced applicants with strong understanding of the RTL2GDSII flow and concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
- Typically requires more than 5 years of relevant industry experience.
- Strong knowledge of physical verification flows and methodology.
- Knowledgeable in partition level P&R implementation, including floorplanning, clock and power distribution, timing closure, physical and electrical verification.
- Knowledge of all aspects of Analog mixed signal physical design.
- Scripting skills to debug flow related issues and make enhancements as appropriate.
- Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
- Real chip tapeout experience with a track record of successful signoff.
- Custom layout design background and experience a plus.
- Hands-on experience with ECO implementation, both functional and timing closure is helpful.
- Excellent interpersonal skills and able to work with multi-functional teams.
- English communication with e-mail is required.
Preferred Qualifications
- Familiar with tapeout of partitions and Verification Flows like LEQ, IR/EM and DFM closure is preferred.
- Verbal communication in English is considered a plus.
- Bachelors of Science, preferred in Electrical Engineering.
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