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Apple Physical Design Engineer STA/Timing Japan, Minato 81925512
02.02.2025
Minimum Qualifications
- We are looking for experienced applicants with strong understanding of the RTL2GDSII flow and concepts related to synthesis, place & route, CTS, timing convergence.
- Typically requires more than 5 years of hands on experience in STA/P&R.
- Familiar with important aspects of timing of large high-performance/low-power SoC designs.
- Proficient in STA and methodologies for timing closure and have a fundamental understanding of noise, crosstalk, and OCV effects, among others.
- Experienced in industry standard tools used for STA such as Synopsys PrimeTime, Cadence Tempus, etc.
- Scripting skills with TCL, Python and Perl to debug flow related issues and make enhancements as appropriate.
- Familiar with worst-case corner selection.
- Experience with STA on large, complex designs and Multi-Scenario Timing Closure.
- Knowledgeable in partition level P&R implementation, including floorplanning, clock and power distribution, timing closure, physical and electrical verification is a plus.
- Familiar with ECO techniques and implementation.
- Good communicator who can accurately describe issues and follow them through to completion.
- English verbal communication is required.
- Bachelors of Science, preferred in Electrical Engineering
Preferred Qualifications
- Familiar with Verification Flows like LEQ, IR/EM, Noise is a plus.
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