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Apple Design Verification DV / Digital Engineer Japan, Minato 806193760
08.02.2025
Description
- You will review design and architecture specifications.- You will understand the functional & performance goals of the design and you use this knowledge to test effectively.- You will communicate and collaborate with digital design, analog design, architecture and firmware teams to understand use cases and corner conditions.- You will develop test plans and coverage plans.- You will work closely with team members and cross-functional teams to execute on verification plans.- You will have the responsibility for construction of verification environments, coding of test scenarios and assertions.- You will write scripts to help with automation and data analysis.- You will run and triage regressions, track bugs, and analyze coverage to achieve quality results.
Minimum Qualifications
- BS/MS required.
- Minimum of 3 years of relevant experience
- Knowledge of Verilog/SystemVerilog, digital simulation and debug
- Knowledge of computer architecture and digital design fundamentals
- Experience with Perl, Python or similar scripting language
- Strong problem solving and analytical skills
- Strong communication skills
Preferred Qualifications
- Strong skills in SystemVerilog with experience crafting verification environments using UVM
- Experience with end-to-end process for SoC digital verification – block and top-level test-planning, constrained random testing, writing and closing coverage
- Ability to work independently to complete project goals
- Experience in formal verification (assertion-based verification) methodology
- Experience with SoC FW verification
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