Cisco Senior ASIC STA Engineer 

United States, California, San Jose 

872148940

The application window is expected to close on: 02/24/2025

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

•This role expects you to be responsible for closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while managing ECO tasks.

•Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA, along with advising the Physical Design team on best practices.

•Additionally, you’ll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.

•Experience in generating timing constraints and performing quality checks such as setup, hold, transition, and noise.

•Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery.

•Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates

•Proficient in synthesis constraints and using industry standard synthesis tools.

•Bachelor’s degree in electrical or computer engineering (or other equivalent field) with 7+ years of related work experience.

•Prior experience using Synthesis Tools: Synopsys DC/DCG/FC.

•Prior experience in Static Timing Analysis & ECO: Synopsys Primetime/Cadence Tempus.

•Prior experience with scripting such as TCL, Perl, or Python.

•Master’s degree in electrical or computer engineering (or other equivalent field) with 4+ years of related work experience.

•Experience using: Synopsys PTPX/Tweaker/PrimeClosure

•Experience using Formal Verification: Synopsys Formality and Cadence LEC.

•Experience using Parasitic Extraction: Synopsys Star-RCXT, Cadence Quantus.