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Nvidia Senior ASIC Design STA Engineer 
India, Karnataka, Bengaluru 
922317421

31.07.2024

What you will be doing:

  • Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff.

  • Take part in top level floor plan and clock planning.

  • Optimize, together with CAD signoff flows and methodologies.

  • Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence.

  • Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency.

What we need to see:

  • B.SC./ M.SC. in Electrical Engineering/Computer Engineering.

  • 3-8 years of experience in physical design and STA

  • Proven experience in RTL2GDS and STA design and convergence

  • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)

  • Hands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required.

  • Great teammate.