מציאת משרת הייטק בחברות הטובות ביותר מעולם לא הייתה קלה יותר
Who you’ll work with
You will collaborate with ASIC Front and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips, working closely with the timing lead on backend timing signoff, including CDC checks, static timing verification, and silicon debugging.
What you’ll do
You will be responsible for closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while managing ECO tasks. Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA, along with advising the Physical Design team on best practices. Additionally, you’ll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.
Minimum Qualifications
Preferred Qualifications
Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart.
משרות נוספות שיכולות לעניין אותך