Nvidia Senior Design Verification Engineer 

United States, California 

805862816

What you’ll be doing:

• Technical leadership role todefine/plan/implement/executeverification strategy of complex design.
• Ability to delve into lowest level details of ASIC design specification, implementation and it's system level impact.
• Interactions with design engineers to define detailed verification scope.
• Draft detailed verification testplans.
• Define/Create a scalable constrained-random verification environment using SystemVerilog and UVM.
• Drive stimulus, comprehensive coverage strategy to show continuous progress towards tape-out.
• Lookout for continuous improvement of verification flows/processes.
• Ability to lead and provide detailed technical guidance junior verification engineers.
• Agility to work on multiple tasks/projects.

What we need to see:

• BS/MS with 8+ years of experience.
• Experience with UVM verification methodology.
• Experience or knowledge with SystemVerilog, SVA or functional coverage.
• Proficient of script language like Perl, Python.
• Experience with silicon bringup.
• Good communication skills and ability & desire to work as a team player are a must.

Ways to stand out from the crowd:

• Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.
• Experience with gate-level simulation, reset verification, contention checking is a plus.
• Experience with Generic IO protocols, I2C, I3C, SPI.
• Ethernet, USB, PCIe is a plus.
• Experience with FPGA is a plus.