Microsoft Senior Design Verification Engineer 

United States, Texas, Austin 

599750628

Required Qualifications:

• 7+ years of technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, or related field AND 4+ years of technical engineering experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, or related field AND 3+ years of technical engineering experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals, including scripting languages such as Python/Perl.
• Background in debugging Register Transfer Level(RTL)Verilog designs as well as simulation and/or emulation environments.
• Experience with verification for product from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C++ and Universal Verification Methodology (UVM).

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• 10+ years of design verification experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental
• Verification experience for an IP or SS related to Central Processing Unit(CPUs), Vision Processing Unit(VPUs), Graphics Processing Units(GPUs), Tensor unit, or similar.
• Knowledge of System Verilog class, constraints, coverage and assertions.
• Experience in scripting languages such as Python or Perl.
• Hands-on experience in Formal property verification, formal verification of computational data path designs.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until July 21, 2024.

In this role you will:

• Perform pre-silicon verification for complex Intellectual Property(IP), including creating testplans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage.
• Interact with architects and design engineers to create testplans covering verification strategy, test requirements, and test environments for IP- or Sub System(SS)-level verification.
• Define verification strategy, requirements, test environments for IP level verification.
• Create testplans and write tests to provide complete features coverage.
• Develop and implement technical solutions to complex quality and design challenges.
• Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage.
• Triage and debug testbench, simulation, and emulation fails.
• Write makefiles and scripts for verification infrastructure.
• Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.
• Collaborate with teams across sites and geographies.
• Other
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