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Microsoft Senior Design Verification Engineer United States 865696263
11.06.2024
Required/Minimum Qualifications
- 7+ years of related technical engineering experience
- OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
- OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
- OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Additional or Preferred Qualifications
- 11+ years technical engineering experience
- OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
- OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
- OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
- 10+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental
- Experience in test plan development to define test cases, checkers, assertions, and functional coverage points.
- Experience in verification of many designs at unit level.
- Knowledge of verification principles, testbenches, UVM, and coverage.
- Knowledge of system verilog class, constraints, coverage and assertions.
- Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
- Proficient in reading, debugging, and/or designing using Verilog languages
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
Microsoft will accept applications for the role until June 11, 2024.
Responsibilities
- Define verification strategy, requirements, test environments for IP level verification.
- Create testplans and write tests to provide complete features coverage.
- Own verification for complex IPs, including creating testplans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage.
- Develop and implement technical solutions to complex quality and design challenges.
- Write scoreboards, sequences, constraints, assertions and functional coverage.
- Write makefiles and scripts for verification infrastructure.
- Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.
- Lead small teams of verification engineers and mentor engineers.
- Collaborate with teams across sites and geographies.
- Embody our
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