Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field and 3 years of experience in the job offered or related occupation.
3 years of experience with each of the following skills is required:
Experience in full chip place and route, top metal layers routing utilizing the industry standard tools like Synopsys ICC/ICC2.
Utilizing TCL/Python for automation of PnR tasks, including chip layout analysis and PDV issues like DRC/LVS.
Experience in Bump/RDL design and top-level integration as part of top-level deliverables.
Experience in electrical issues involving Bump/RDL design for power delivery and chip functionality.
Utilizing Calibre for all layout verification like LVS/DRC/Antenna, including experience in layout quality and fixes.
Utilizing device physics including device and transistor knowledge to understand bottle necks in design.