Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering or related field, and 2 years experience in the job offered or related occupation.
Experience and/or education with each of the following skills:
Scripting to parse large reporting and collect design data for statistical analysis.
Understanding of VLSI Design principles (floor planning / placement and clock tree synthesis) to handle physical design aspects of CPU core.
Logic Design principles for understanding and ensuring efficient transferring of RTL to gate logic.
Working in Timing static analysis tool and understanding of the timing engine concepts (delay calc /crosstalk)
Constraining the design in timing analysis engine and understanding of functional logic to add exceptions, and working with design verification team.
Programming skills to develop and enhance timing analysis flow and graphical dashboard for monitoring timing metrics.
Understanding of device physics, timing and noise impacts from logic cell architectures on latest technology nodes