Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering or related field and 2 years of experience in the job offered or related occupation.
2 years of experience with each of the following skills is required:
Experience in Electronic Design Automation tool for Synthesis, Scan Insertion and Logic Equivalence flow development.
Static Timing Analysis (STA) experience using Prime Time
Experience in Logic design and experience implementing manual design changes.
Experience in semiconductor device physics and transistor-level circuit design.
Experience in developing flows to increase the chip's reliability, including experience in scan insertion, JTAG top-level integration, formal verification, clock domain crossing, and Logic equivalence checks.
Using PnR tools Cadence Innovus and Synopsys ICC Compiler for physical implementation of modules and closure of design.
Using Object-oriented programming, System Verilog, Python, TCL, and algorithms, including writing automation scripts and improving efficiency.
Using HSpice to conduct gate-level simulations.
Using Cadence Conformal to confirm logical equivalence between RTL and design.
Understanding of industry-standard implementation practices of the entire design flow, from conceptualization to fabrication.
Experience collaborating with cross-functional teams, including architects, designers, verification, and manufacturing engineering teams.