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Cisco Senior Technical Leader ASIC Engineering 
United States, California, San Jose 
68048668

29.07.2024

שיתוף

התחבר/י כדי להגיש מועמדות

What You'll Do

The Core Hardware Business Unit is looking for a motivated Senior Verification engineer/lead to engage in new development of our UCS family. You will have an ASIC design and verification background with hands-on experience in RTL verification and in-depth knowledge of SoC development cycle and the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume semiconductor markets.

What you'll do

  • Architect block, cluster and top level DV environment infrastructure
  • Create DV infrastructure from scratch for block, cluster and top level environments
  • Maintaining existing DV environments and enhancing them
  • Ensuring complete verification coverage through implementation and review of code and functional coverage
  • Working closely with designers
  • Supporting tests done with emulation
  • Work closely with software teams and debug issues found during firmware development
  • Be responsible for ASIC bring up

Who You Are

12+ years ASIC design verification experience and collaborate closely with verification engineers, designers, hardware & cross functional teams to verify the ASIC in simulation, in emulation and during ASIC bring up.

Minimum requirements

  • Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 12 years of experience in ASIC Design
  • ASIC verification using UVM/System Verilog.
  • Prior experience in verifying complex blocks, clusters and top level for SoC
  • Build testbenches from scratch, hands on experience with System Verilog constraints, structures and classes.
  • Scripting with Perl and/or Python
  • Experience in collaborating with cross-functional teams, and possess the drive to learn and grow
  • Prior domain experience on one or more protocols – PCIe, Ethernet, RDMA, TCP, FC
  • You have lead a team of engineers to complete verification of a complex block, cluster or chip-level design

Preferred Skills

  • Lead verification for a complete SOC or ASIC
  • Experience with Forwarding logic/Parsers/P4
  • Experience with Veloce/Palladium/Zebu/HAPS
  • Prior verification experience (iev/vc formal) knowledge

We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).

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