Cisco ASIC Engineering Technical Leader 

United States, California, San Jose 

211164155

What You'll Do

The Core Hardware Business Unit is looking for a motivated Senior Verification engineer/lead to engage in new development of our UCS family. You will have an ASIC design and verification background with hands-on experience in RTL verification and in-depth knowledge of SoC development cycle and the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume semiconductor markets.

• Architect block, cluster and top level DV environment infrastructure
• Create DV infrastructure from scratch for block, cluster and top level environments
• Maintaining existing DV environments and enhancing them
• Ensuring complete verification coverage through implementation and review of code and functional coverage
• Working closely with designers
• Supporting tests done with emulation
• Work closely with software teams and debug issues found during firmware development

Minimum Qualifications:

• 10+ years ASIC design verification experience with a Bachelor’s or Master’s degree

• Prior experience with ASIC verification using UVM/System Verilog.
• Priorexperiencein verifying complex blocks, clusters and top level for SoC
• Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
• Prior experience with cross-functional teams, and possess the drive to learn and grow
• Prior experience on one or more protocols – PCIe, Ethernet, RDMA, TCP

Preferred Qualifications:

• Lead a team of engineers to complete verification of a complex block, cluster or chip-level design
• Lead verification for a complete SOC or ASIC i
• Prior Experience with Forwarding logic/Parsers/P4
• Formal verification (iev/vc formal) knowledge