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Cisco Senior ASIC Design Engineer United States, California, San Jose 667693565
27.01.2025
The application window is expected to close on: February 10, 2025.
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
This role requires being onsite in San Jose, CA 4+ days/week.
Your Impact
- Author design specifications and participate in micro-architecture specification reviews.
- Implement Verilog RTL to meet timing, performance, and power requirements
- Help define, evolve, and support our design methodology.
- Develop and analyze functional coverage.
- Collaborate with the verification team to address design bugs and close code coverage.
- Work closely with physical design team to close design timing and place-and-route issues.
- Triage, debug, and root cause simulation, software bring-up, and customer failures.
- Perform diagnostic and post silicon validation tests in the lab.
Minimum Qualifications
- Bachelor’s degree in Electrical or Computer engineering and 7+ years of ASIC Design experience.
- Experience with Verilog/System Verilog
- Interactive and waveform debug experience.
- Experience resolving setup and hold timing violations with RTL modification.
Preferred Qualifications
- Master’s degree in Electrical or Computer engineering and 4+ years of ASIC Design experience.
- Scripting experience (Python, Perl, TCL, shell programming).
- Good written and verbal communication skills.
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