Cisco Senior ASIC Design Engineer 

United States, California, San Jose 

639580963

The application window is expected to close on: for U.S. March 7, 2025

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Your Impact

* Write micro-architecture specifications and participate in reviews.

* Implement Verilog RTL to meet timing, performance, and power requirements.

* Contribute to full chip integration and timing methodology/analysis.

* Develop and analyze functional coverage.

* Help define, evolve, and support our design methodology.

* Collaborate with the verification team to address design bugs and close code coverage.

* Work closely with the physical design team to close design timing and place-and-route issues.

* Triage, debug, and root cause simulation, software bring-up, and customer failures

* Perform diagnostic and post-silicon validation tests in the lab

Minimum Qualifications:

* Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC design experience or Master's Degree in Electrical or Computer Engineering with 4+ years of ASIC design experience.

* Prior experience working with Verilog or System Verilog programming skills

* Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime)

* Experience with debugging and verification methodologies

Preferred Qualifications:

* Understanding of Networking technologies and concepts

* Scripting experience (Python, Perl, TCL, shell programming)

* Experience with formal verification tools

* Experience with emulation