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Cisco Technical Leader ASIC Design United States, California, San Jose 644565991
Yesterday
The application window is expected to close on: 05/15/2025.
The job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Your Impact
As a diligent FPGA Prototyping Engineer with exceptional analytical skills, you excel in utilizing industry-standard FPGA prototyping tools and have a proven ability to map multi-million gate SoCs to FPGAs. You will collaborate closely with Design, DV, and Software teams to understand chip architecture and effectively prototype the SoC on the FPGA platform. Your contributions will be integral to the development of next-generation networking chips.
Responsibilities include:
- Be part of the development organization as an ASIC Engineering Technical Leader with primary focus on FPGA Prototyping
- Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components
- Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology
- Option to engage in block-level RTL design or block or top-level IP integration
- Collaborate with Software, Design, and Verification teams to validate the functional and performance objectives of the SoC
Minimum Qualifications:
- A Bachelor's Degree in Electrical or Computer Engineering, accompanied by a minimum of 10 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline
- A comprehensive understanding of FPGA design, with proven expertise in partitioning multi-million gate designs across multiple FPGAs.
- Proficiency in synthesis, place, and route flows for FPGAs.
- An in-depth knowledge of digital design concepts, including Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
- Demonstrated experience in RTL coding using Verilog/System Verilog and integration of third-party IPs.
- A meticulous and methodical approach to triaging, debugging, and identifying root causes of issues throughout various phases of FPGA development
Preferred Qualifications:
- Experience in prototyping Networking System-on-Chips (SoCs) on HAPS or equivalent prototyping platforms
- A strong understanding of PCIE, DDR, Ethernet, and Networking Protocols
- Proficiency in prototyping ARM or RISCV CPUs
- Exceptional scripting skills using languages such as TCL, Python, or Perl
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