Cisco ASIC Physical Design Technical Leader 

United States, California, San Jose 

227318062

Your Impact

You'll be joining our Physical Design team at
Cisco Silicon Onegroup, which is responsible for the entire development process of RTL to GDS, leading development of high quality VLSI designs. Responsibilities include:

• Fullchip Floorplan and Partition/Pin assignment.
• Fullchip Clock Planning (Experience with both H-Tree and Clock Mesh architectures).
• Interface with Fullchip STA team on timing constraints.
• Power Planning and Robust Power Grid planning for lower technology nodes.
• Fullchip Physical Verification.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering or equivalent similar experience.
• 10+ years of experience in Physical Design.
• Experience working on Fullchip activities.
• Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies.
• Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre.

Preferred Qualifications

• Exposure to static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
• Experience in Full-chip floor-planning and power grid planning.
• Experience with custom clock (H-Tree or Mesh) at chip level
• Experience with Python, TCL, Perl programming.
• Leadership/Mentorship experience.