ARM Senior STA Engineer 

United States, California, San Jose 

605274855

• Owning full chip and block level timing closure throughout the entire project cycle for complex multi-instantiated designs
• Handling timing constraints for functional and test mode at different logical hierarchical levels
• Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs
• ECO generation at both block and top level, handshaking with team for timing/functional ECO implementation
• Familiarity with IO interfaces and SOC bus protocols

• Work experience of 6+ years in Timing convergence
• Experience in industry standard STA tools and methodologies
• Knowledge of timing corners/modes including DFT, process variations and signal integrity issues
• Work experience on timing closure for multi power domain designs
• Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors
• Must have worked on constraints development and timing closure on 5nm or 3nm technologies
• Strong Automation(Pert/Tcl/Python) and conversational abilities

• Masters in Electrical Engineering
• Coding skills in Perl/Python or TCL or an equivalent language
• Familiarity with synthesis, logic equivalence, DFT, CLP and backend related methodology and tools
• Strong presentation skills

We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding.

• Partner and customer focus
• Teamwork and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises