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Apple Digital Design Engineer United States, California, Cupertino 577646541
Today
- Master’s degree or foreign equivalent in Electrical Engineering, Electronic Engineering or related field and 1 year of experience in the job offered or related occupation.
- 1 year experience in each of the following skills:
- Utilizing System Verilog or Verilog to wrote RTL for the high speed communication IPs
- Utilizing Scripting language (Python, Perl, or TCL), including automating the RTL integration flow, process verification, synthesis and timing reports, and building hardware models.
- Utilizing CDC, RDC tools/techniques, and knowledge of multiple clock domains, multiple reset domains and fixing issues.
- Knowledge in RTL Design with complex FSMs, and power saving features.
- Knowledge in IP Integration including clock/reset module design, clock/power gating implementation, fabric/bus system configuration and design.
- Industry low power methodologies including UPF/CPF and low power check techniques.
- High speed interface design (source synchronous bus, SerDes)
- Utilizing Synthesis tools from Synopsys, Cadence and setting the correct constraints for synthesis, and knowledge of LEC/LEQ tools and doing ECOs
- Knowledge of computer architecture and SOC’s
- Low power design concepts and implementation, including clock gating, power gating, and DVFS.
- Knowledge of modern wireless communication theory and concepts
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