Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field and 4 years of experience in the job offered or related occupation.
4 years of experience with each of the following skills is required:
Using Verilog and SystemVerilog to implement custom models in RTL.
Using simulators VCS, and using waveform debugging tools such as Verdi to test the RTL functionality.
Using regressions and revision control tools to maintain the RTL in a version-controlled fashion.
Using special modeling modes such as power-aware and X/Z modeling in the design.
Writing assertions to cover illegal cases.
Using scripting in languages Perl or Python to speed up RTL development.
Qualifying RTL through lint tools, jasper formal sanity for combo loops and functional DV.
DFT (Design for Testability) validation support including ATPG (Automatic Test Pattern Generation) pattern simulations and debug.