Nvidia Digital Circuit Design Engineer 

Taiwan, Taiwan Province, Hsinchu 

130538706

As a member of our Mixed-Signal high-speed I/O SerDes group, you'll be working on NVDIA's latest ground breaking technology that enables and accelerates gaming, artificial intelligence, deep learning, and autonomous driving. Your design will be consumed by standard as well as industry-leading proprietary high-speed protocols, and will serve as one of the key IPs in many complex SoC. You'll work closely with analog designers and system architects to independently come up with micro-architecture specification and refine adaptation algorithms. You'll then implement the RTL in SystemVerilog, define test cases that will deeply verify the design and carry out test creations. Next is to define and build constraints for synthesis and drive for timing closure. In addition to RTL design, you'll need to understand the analog schematics and write SystemVerilog models that collects the functionality of those circuits in the most precise way.

What you'll be doing:

• Be actively involve in developing mixed-signal chips .

• Plan the specification, evaluate the PPA of algorithms, design the digital circuits such as filters and analog calibration circuits

• Verify the analog and digital design using direct test and random test

• Perform the frond-end design flows(Lint/CDC/Synthesis/DFT/LEC/STA)and co-work with back-end team to chip tape-out

• Help in silicon bring-up and fine-tune performance

What we need to see:

• You should have a B.S. or MS degree in Electrical Engineering or equivalent experience, 3+ years of experience is preferred.

• Experiencein high-speed SerDes I/O digital design, knowledge at protocol level (Ethernet, PCIE) preferred.

• Have a deep understanding of Verilog or SystemVerilog, logic design and circuit modeling in RTL for mixed-signal blocks; Experience with industry standard verification methodologies, such as UVM.

• Proven experience with custom digital circuit design and adaptation algorithms, such as FFE, DFE, CTLE, CDR, and offset cancellation.

• Experience with static timing tools and formal verification tools.

• Have a strong background in Perl and Python scripting; If you have a background in computer architecture and deep learning, this is a plus.